Ganesh Kiran

20220368299, Nov 17, 2022

May 13, 2021

17/320077

- San Diego CA, US
Aram Akhavan - San Diego CA, US
Ganesh Kiran - San Diego CA, US
Lei Sun - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US
Dinesh Jagannath Alladi - San Diego CA, US

H03G 3/30
H03M 1/12
H03F 3/19
H03F 3/21

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

20230046277, Feb 16, 2023

Aug 16, 2021

17/403683

- San Diego CA, US
Kentaro YAMAMOTO - San Diego CA, US
Lei SUN - San Diego CA, US
Ganesh KIRAN - San Diego CA, US

H03M 1/16
H03F 3/45
H03M 1/12

Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

20200212904, Jul 2, 2020

Apr 30, 2019

16/399630

- San Diego CA, US
Ganesh Kiran - San Diego CA, US
Seyed Arash Mirhaj - San Diego CA, US

H03K 17/041

A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.

20170093420, Mar 30, 2017

Feb 3, 2016

15/014865

- San Diego CA, US
Liang DAI - San Diego CA, US
Ganesh KIRAN - San Diego CA, US

H03M 1/38
H03M 1/10

Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

20160181983, Jun 23, 2016

Dec 19, 2014

14/577950

- San Diego CA, US
Ganesh Kiran - San Diego CA, US

H03F 1/02
H03F 1/22
H03F 3/45

A low power operational transconductance amplifier is disclosed. In an exemplary embodiment, an apparatus includes a transconductance stage configured to convert a first input voltage signal to first and second current signals and to convert a second input voltage signal to third and fourth current signals. The apparatus also includes a current amplification stage configured to amplify the second current signal to generate a first amplified current signal and to amplify the fourth current signal to generate a second amplified current signal. The apparatus also includes a current summation stage configured to sum together the third current signal and the first amplified current signal to generate a first output voltage signal, and to sum together the first current signal and the second amplified current signal to generate a second output voltage signal.