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Galen E Stansell

from Kirkland, WA
Age ~53
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Related to:
Leroy Wentz, 91Le Roy Wentz, 92Susan M Lovelace, 54Sharon R Lopez, 60
Connected to:
Adam C Stansell, 29Aileen D Stansel, 58Ben N Stansell, 63Bobby Stansell, 53Brandy M Stansell, 42Bryan R Stansel, 55Caitlin E Stansel, 33David J Stansell, 81Deanna L Stansell, 59Deborah Stansel, 47

Galen Stansell Phones & Addresses

  • 12400 106Th Pl NE, Kirkland, WA 98034 (425) 823-2725
  • Buckley, WA

Work

Company: Cypress semiconductor Apr 1995 Position: Design engineer mts

Education

Degree: BSEE School / High School: University of Washington 1990 to 1995 Specialities: Electrical Engineering

Skills

Semiconductors • Mixed Signal • Debugging • Ic • Analog • Cmos • Soc • Asic • Verilog • Embedded Systems

Industries

Semiconductors

Resumes

Resumes

Galen Stansell Photo 1

Director Of Design Engineering

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Location:
709 Mountain View Ave, Buckley, WA 98321
Industry:
Semiconductors
Work:
Cypress Semiconductor since Apr 1995
Design Engineer MTS
Education:
University of Washington 1990 - 1995
BSEE, Electrical Engineering
Skills:
Semiconductors
Mixed Signal
Debugging
Ic
Analog
Cmos
Soc
Asic
Verilog
Embedded Systems

Publications

Us Patents

Clock Generator With Programmable Two-Tone Modulation For Emi Reduction

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US Patent:
6373306, Apr 16, 2002
Filed:
Oct 12, 2000
Appl. No.:
09/689492
Inventors:
Eric N. Mann - Issaquah WA
Galen E. Stansell - Kirkland WA
Monte F. Mar - Issaquah WA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03L 700
US Classification:
327159, 327150, 327156, 327147, 327131
Abstract:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.

Loadable Divide-By-N With Fixed Duty Cycle

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US Patent:
6501815, Dec 31, 2002
Filed:
Jun 30, 2000
Appl. No.:
09/607697
Inventors:
Galen Stansell - Kirkland WA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 2100
US Classification:
377 47, 377 48
Abstract:
A circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.

Multi-Modulus Counter In Modulated Frequency Synthesis

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US Patent:
6559726, May 6, 2003
Filed:
Oct 31, 2001
Appl. No.:
09/999743
Inventors:
Galen E. Stansell - Kirkland WA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03L 718
US Classification:
331 16, 331 1 A, 331 25, 327117, 327156, 327159, 327115
Abstract:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.

Robust Clock Circuit Architecture

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US Patent:
6674332, Jan 6, 2004
Filed:
Sep 6, 2002
Appl. No.:
10/236475
Inventors:
John J. Wunner - Woodinville WA
Galen E. Stansell - Kirkland WA
Assignee:
Cypress Semiconductor, Corp. - San Jose CA
International Classification:
H03L 706
US Classification:
331 18, 331 2, 331 16, 331 25, 327292
Abstract:
In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e. g. , phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Method And Apparatus For Converging A Control Loop

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US Patent:
6798297, Sep 28, 2004
Filed:
Nov 20, 2002
Appl. No.:
10/301768
Inventors:
King H. Kwan - Bellevue WA
Galen E. Stansell - Kirkland WA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L 708
US Classification:
331 10, 331 17, 331 25, 327156
Abstract:
In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e. g. , substantially zero), thus allowing for relatively short loop convergence time.

Anti-Fuse Latch Circuit And Method Including Self-Test

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US Patent:
7339848, Mar 4, 2008
Filed:
Jan 30, 2006
Appl. No.:
11/343341
Inventors:
Galen Stansell - Kirkland WA, US
Frederick Jenne - Sunnyvale CA, US
Igor Kouznetzov - Sunnyvale CA, US
Ken Fox - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 17/18
US Classification:
3652257, 365200, 365201
Abstract:
A programmable latch circuit () can include a programmable data circuit () with a data load path () that can enable a data value to be recalled into a volatile latch (). A data load path () can be formed with devices (P-P) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.

Device And Method For Sensing Programming Status Of Non-Volatile Memory Elements

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US Patent:
7426142, Sep 16, 2008
Filed:
May 1, 2006
Appl. No.:
11/415694
Inventors:
Galen E. Stansell - Kirkland WA, US
Tomasz Cewe - Bothell WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 16/06
US Classification:
36518521, 365201, 36518907, 3652257
Abstract:
A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements can be determined to be programmed. In particular embodiments, non-volatile elements can be sections of differential one-time programmable anti-fuse latch memory elements.

Well Bias Architecture For Integrated Circuit Device

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US Patent:
7598794, Oct 6, 2009
Filed:
Sep 25, 2007
Appl. No.:
11/904246
Inventors:
Galen E. Stansell - Kirkland WA, US
King Eric Kwan - Bellevue WA, US
Xiaolin Ouyang - Seattle WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 3/01
US Classification:
327534, 327434
Abstract:
Disclosed is a high voltage switch circuit that can include a first well bias switch configured to track the greater of an input voltage and a supply voltage, a voltage comparator configurable to compare the input voltage to a predetermined reference voltage, and a second well bias switch having a control input coupled to an output of the comparator.
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Galen E Stansell from Kirkland, WA, age ~53 Get Report