Resumes
Resumes
Gadiel Seroussi Phones & Addresses
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1123 Milky Way, Cupertino, CA 95014 (408) 257-9663
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Venice, CA
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Los Angeles, CA
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Oakland, CA
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Coyote, CA
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San Jose, CA
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1123 Milky Way, Cupertino, CA 95014 (408) 218-0296
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Emails
Publications
Us Patents
Optimizing Computer Performance By Using Data Compression Principles To Minimize A Loss Function
View pageUS Patent:
6453389, Sep 17, 2002
Filed:
Jun 25, 1999
Appl. No.:
09/340279
Inventors:
Marcelo Weinberger - San Jose CA
Tomas G. Rokicki - Palo Alto CA
Gadiel Seroussi - Cupertino CA
Rajiv Gupta - Los Altos CA
Neri Merhav - Haifa, IL
Joesp M. Ferrandiz - Palo Alto CA
Tomas G. Rokicki - Palo Alto CA
Gadiel Seroussi - Cupertino CA
Rajiv Gupta - Los Altos CA
Neri Merhav - Haifa, IL
Joesp M. Ferrandiz - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1200
US Classification:
711137, 711213
Abstract:
The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched. This stall time is modeled as a loss function of the form: The weights in the data structure change as the prefetch engine learns more information. The prefetch engines goal is to predict the cache line needed and prefetch before the CPU requests it.
Apparatus And Method For Efficient Arithmetic In Finite Fields Through Alternative Representation
View pageUS Patent:
6466959, Oct 15, 2002
Filed:
Feb 26, 2001
Appl. No.:
09/751438
Inventors:
Ian F. Blake - Palo Alto CA
Ron M. Roth - Ramat Gan, IL
Gadiel Seroussi - Cupertino CA
Ron M. Roth - Ramat Gan, IL
Gadiel Seroussi - Cupertino CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 700
US Classification:
708492
Abstract:
A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format. Thus, efficient arithmetic is obtained by using the most efficient algorithm available in either the first representation format or the alternative representation format and permuting operands and results to the representation format corresponding to the most efficient algorithm available.
Decoding Of Embedded Bit Streams Produced By Context-Based Ordering And Coding Of Transform Coeffiecient Bit-Planes
View pageUS Patent:
6510247, Jan 21, 2003
Filed:
Dec 17, 1998
Appl. No.:
09/213743
Inventors:
Erik Ordentlich - Palo Alto CA
Marcelo Weinberger - San Jose CA
Gadiel Seroussi - Cupertino CA
Marcelo Weinberger - San Jose CA
Gadiel Seroussi - Cupertino CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06K 936
US Classification:
382232, 382236, 382240, 382248
Abstract:
A method of decoding an embedded bitstream includes the steps of reading encoded subsequences in the bitstream as ordered, decoding at least some of the ordered subsequences, and combining the subsequences to obtain reconstructed data. The encoded subsequences are read in order of decreasing expected distortion reduction per expected bit of description.
Burst Error And Additional Random Bit Error Correction In A Memory
View pageUS Patent:
6532565, Mar 11, 2003
Filed:
Nov 15, 1999
Appl. No.:
09/440323
Inventors:
Ron M. Roth - Haifa, IL
Gadiel Seroussi - Cupertino CA
Ian F. Blake - Toronto, CA
Gadiel Seroussi - Cupertino CA
Ian F. Blake - Toronto, CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H03M 1300
US Classification:
714761, 714762, 714787
Abstract:
A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.
Access Control Through Secure Channel Using Personal Identification System
View pageUS Patent:
6836843, Dec 28, 2004
Filed:
Jun 29, 2001
Appl. No.:
09/896796
Inventors:
Gadiel Seroussi - Cupertino CA
Kenneth Graham Paterson - Bristol, GB
Wenbo Mao - Bristol, GB
Mark T. Smith - San Mateo CA
Kenneth Graham Paterson - Bristol, GB
Wenbo Mao - Bristol, GB
Mark T. Smith - San Mateo CA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H04L 932
US Classification:
713173, 380 29, 380 30, 455 39, 235380, 3405391, 3405721
Abstract:
A security system based on a tamper resistant badge that becomes deactivated if the badge is removed from the person authorized to wear the badge. The badge has a volatile memory for storing the security clearance information associated with the wearer and a processor having sufficient power to perform encrypted communications. The badge also has an attachment sensor that resets the security clearance information if the badge is removed from the wearer. A secure data processing system utilizing the badges includes an administrative computer, A, and a client computer, C. Computer A has an identity verification system for authenticating the identity of individuals having badges and loading the clearance information into the volatile memory after the badge is attached to the wearer. The C computers access the information in the badges volatile memory to provide access to the wearer at the access level specified in the volatile memory.
Data Storage Method For Use In A Magnetoresistive Solid-State Storage Device
View pageUS Patent:
6981196, Dec 27, 2005
Filed:
Jul 25, 2001
Appl. No.:
09/915195
Inventors:
James A Davis - Richmond VA, US
Jonathan Jedwab - Bristol, GB
Kenneth Graham Paterson - Teddington, GB
Gadiel Seroussi - Cupertino CA, US
Kenneth K Smith - Boise ID, US
Jonathan Jedwab - Bristol, GB
Kenneth Graham Paterson - Teddington, GB
Gadiel Seroussi - Cupertino CA, US
Kenneth K Smith - Boise ID, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C029/00
US Classification:
714763
Abstract:
A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. Since currently available MRAM devices are subject to physical failures, data storage arrangements are described to minimize the affect of those failures on the stored ECC encoded data, including storing all bits of each symbol in storage cells in one row (FIG. ), or in at least two rows but using storage cells in the same columns (FIG. ). Sets of bits taken from each row are allocated to different codewords (FIG. ) and the order of allocation can be rotated (FIG. ). A second level of error checking can be applied by adding a parity bit to each symbol (FIG. ).
Method For Error Correction Decoding In An Mram Device (Historical Erasures)
View pageUS Patent:
6990622, Jan 24, 2006
Filed:
Mar 8, 2002
Appl. No.:
10/093854
Inventors:
James Andrew Davis - Richmond VA, US
Jonathan Jedwab - London, GB
Kenneth Graham Paterson - Teddington, GB
Gadiel Seroussi - Cupertino CA, US
Jonathan Jedwab - London, GB
Kenneth Graham Paterson - Teddington, GB
Gadiel Seroussi - Cupertino CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 29/00
US Classification:
714763, 714759, 714746, 714752
Abstract:
A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns of an array of storage cells which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder to perform ECC decoding is substantially enhanced.
Method And System For Minimizing The Length Of A Defect List For A Storage Device
View pageUS Patent:
7013378, Mar 14, 2006
Filed:
Apr 30, 2003
Appl. No.:
10/427526
Inventors:
Giovanni Motta - Waltham MA, US
Erik Ordentlich - San Jose CA, US
Gadiel Seroussi - Cupertino CA, US
Marcelo Weinberger - San Jose CA, US
Erik Ordentlich - San Jose CA, US
Gadiel Seroussi - Cupertino CA, US
Marcelo Weinberger - San Jose CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 12/16
US Classification:
711203, 711100, 711154, 711200, 714 8
Abstract:
A number of methods and systems for efficiently storing defective-memory-location tables. A asymmetrical-distortion-model vector quantization method and a run-length quantization method for compressing a defective-memory-location bit map that identifies defective memory locations within a memory are provided. In addition, because various different compression/decompression methods may be suitable for different types of defect distributions within a memory, a method is provided to select the most appropriate compression/decompression method from among a number of compression/decompression methods as most appropriate for a particular defect probability distribution. Finally, bit-map compression and the figure-of-merit metric for selecting an appropriate compression technique may enable global optimization of error-correcting codes and defective memory-location identification.