Chong Hsing Lee

6650140, Nov 18, 2003

Mar 6, 2002

10/093785

Chong H. Lee - San Ramon CA
Reza Asayesh - Menlo Park CA

Altera Corporation - San Jose CA

H03K 19177

326 39, 326 38

A programmable logic device (âPLDâ) includes high speed serial interface (âHSSIâ) circuitry that can support several high speed serial (âHSSâ) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

6653860, Nov 25, 2003

Aug 10, 2001

09/927793

Om P. Agrawal - Los Altos CA
Xiaojie (Warren) He - Austin TX
Claudia A. Stanley - Austin TX
Larry R. Metzger - Austin TX
Chong M. Lee - Colorado Springs CO

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19177

326 41, 326 38

An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PTs) therefrom. Part or all of the macrocells local 5 PTs may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoPs generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PTs (e. g. , 5 PTs) to having slower generation of sums of a much larger number of PTs (e. g.

6724328, Apr 20, 2004

Jun 3, 2003

10/454626

Henry Y. Lui - San Jose CA
Chong H. Lee - San Ramon CA
Rakesh Patel - Cupertino CA
Ramanand Venkata - San Jose CA
John Lam - Union City CA
Vinson Chan - Fremont CA
Malik Kabani - Mountain View CA

Altera Corporation - San Jose CA

H03M 900

341101, 710 71

A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

6750675, Jun 15, 2004

Jul 11, 2002

10/195229

Ramanand Venkata - San Jose CA
Chong H. Lee - San Ramon CA
Rakesh Patel - Cupertino CA

Altera Corporation - San Jose CA

A03K 19177

326 41, 326 37, 326 47

A programmable logic device (âPLDâ) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (âPOS-5â) and 8-bit/10-bit (â8B10Bâ) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

6771105, Aug 3, 2004

Mar 13, 2002

10/099707

Stjepan William Andrasic - Burlingame CA
Rakesh H. Patel - Cupertino CA
Chong H. Lee - San Ramon CA

Altera Corporation - San Jose CA

H03H 1126

327276, 327266, 327280, 331 57

A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (âVCOâ) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (âPLLâ) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

6842034, Jan 11, 2005

Jul 1, 2003

10/612253

Vinson Chan - Fremont CA, US
Chong Lee - San Ramon CA, US
Rakesh Patel - Cupertino CA, US
Ramanand Venkata - San Jose CA, US
Binh Ton - San Jose CA, US

Altera Corporation - San Jose CA

H03K 1900

326 8, 326 37, 326 39

Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

6854044, Feb 8, 2005

Dec 10, 2002

10/317262

Ramanand Venkata - San Jose CA, US
Chong H. Lee - San Ramon CA, US

Altera Corporation - San Jose CA

G06F012/00

711201, 341101

Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.

6867616, Mar 15, 2005

Jun 4, 2003

10/455773

Ramanand Venkata - San Jose CA, US
Chong H. Lee - San Ramon CA, US
Rakesh Patel - Cupertino CA, US

Altera Corporation - San Jose CA

H03K019/173
H03D003/24

326 41, 326 47, 375376

In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.