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Freeman D Colbert

from Chandler, AZ
Age ~67
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Also known as:
Freeman Evangeline Colbert, Evangeline B Colbert, Durand Colbert Freeman, Evangeline Colbert Tr, Andre Colbert
Phone and address:
2064 Longhorn Dr, Chandler, AZ 85248
(480) 821-9268
Related to:
Simone Colbert, 30
Connected to:
Agatha P Colbert, 79Al Colbert, 52Andre D Colbert, 55Anna M Colbert, 64Apollonia K Colbert, 38Asia Colbert, 32Aundrea Colbert, 42Bennie D Colbert, 55Bryce D Colbert, 34Caritas J Colbert, 43

Freeman Colbert Phones & Addresses

  • 2064 Longhorn Dr, Chandler, AZ 85248 (480) 821-9268
  • 538 Silver Creek Rd, Gilbert, AZ 85233 (480) 892-4787
  • Mesa, AZ
  • Scottsdale, AZ
  • Maricopa, AZ
  • 2064 W Longhorn Dr, Chandler, AZ 85286 (480) 235-1338

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Resumes

Resumes

Freeman Colbert Photo 1

Product Engineering Manager

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Location:
Chandler, AZ
Industry:
Semiconductors
Work:
Motorola Semiconductor Products Sector Sep 1980 - Jan 1996
Logic Design Engineer
Microchip Technology Sep 1980 - Jan 1996
Product Engineering Manager
Education:
Georgia Institute of Technology 1979 - 1980
Masters, Electronics Engineering Georgia Institute of Technology 1974 - 1979
Bachelors, Electronics Engineering Georgia Institute of Technology 1975 - 1979
Masters Warner Robin's High School 1970 - 1974
Skills:
Technical Leadership
Cross Functional Team Leadership
Analytic Problem Solving
Project Management
Program Management
Semiconductors
Test Engineering
Mixed Signal
Verification and Validation
Device Characterization
Quality Control
Cmos
Languages:
English
Freeman Colbert Photo 2

Technical Staff Engineer

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Microchip Technology
Technical Staff Engineer

Business Records

Name / Title
Company / Classification
Phones & Addresses
Freeman D Colbert
Director
SON RISE FAITH COMMUNITY CENTER, INC
1926 W Aspen Ave, Gilbert, AZ 85233
Director 2064 W Longhorn Dr, Chandler, AZ 85248
Freeman Colbert
Manager
ADVANCE BUSINESS ENTERPRISES, LLC
2064 W Longhorn Dr, Chandler, AZ 85248

Publications

Us Patents

Cmos Output Driver Which Can Tolerate An Output Voltage Greater Than The Supply Voltage Without Latchup Or Increased Leakage Current

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US Patent:
54518890, Sep 19, 1995
Filed:
Mar 14, 1994
Appl. No.:
8/209891
Inventors:
Barry B. Heim - Mesa AZ
Paul T. Hu - Tempe AZ
Deborah Beckwith - Chandler AZ
Freeman D. Colbert - Gilbert AZ
MonaLisa Morgan - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 190175
US Classification:
326 81
Abstract:
A mixed mode buffer circuit 11 including a first input (12), a second input (13), and an output (14). A voltage exceeding a supply voltage of mixed mode buffer circuit 11 can be applied to the output (14) without latchup or an increase in leakage current. The mixed mode buffer includes an output transistor (24) of a first conductivity type having a first electrode coupled to the output (14), a control electrode coupled to the first input (12), a second electrode coupled for receiving the supply voltage, and a bulk electrode. A first transistor (19) biases the bulk electrode when the voltage at the output is within a first predetermined range. A first bulk bias circuit (28) biases the bulk electrode when the output voltage is within a second predetermined range. A second bulk bias circuit (27) and a second transistor (18) couples the voltage at the output to the bulk electrode and the control electrode respectively, when the output voltage exceeds the second predetermined range.

Method For Forming An Electrostatic Discharge Protection Device

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US Patent:
55977588, Jan 28, 1997
Filed:
Aug 1, 1994
Appl. No.:
8/283437
Inventors:
Barry B. Heim - Mesa AZ
Freeman D. Colbert - Gilbert AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21265
H01L 2170
H01L 2700
US Classification:
437 60
Abstract:
An ESD protection device and a method for forming the ESD protection device in an active region (13) which is devoid of a field oxide (14). A P type dopant region (22) and an N type dopant region (27) are formed in a semiconductor substrate (11) using photolithographic techniques, wherein they are spaced apart from each other by a spacer region (29). An anode electrode (33) contacts the P type dopant region (22) and a cathode electrode (34) contacts the N type dopant region (27). A parasitic diode resistance of the ESD protection device is governed by the width of the spacer region (29) which, in turn, is governed by the resolution of the photolithographic techniques. Thus, the present invention provides a method for lowering both the parasitic diode resistance and clamp voltage of the ESD protection device which serves to protect integrated circuits from large voltage transients.
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Freeman D Colbert from Chandler, AZ, age ~67 Get Report