Frederick W Perner

6363000, Mar 26, 2002

Apr 5, 2001

09/827114

Frederick A Perner - Palo Alto CA
Kenneth J Eldredge - Boise ID
Lung T Tran - Saratoga CA

Hewlett-Packard Company - Palo Alto CA

G11C 508

365 66, 365173

A write circuit for a large array of memory cells of a Magnetic Random Access Memory (âMRAMâ) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

6456524, Sep 24, 2002

Oct 31, 2001

10/000636

Frederick A. Perner - Palo Alto CA
Lung Tran - Saratoga CA

Hewlett-Packard Company - Palo Alto CA

G11C 1100

365158, 365148

A data storage device that includes a novel resistive cross point memory cell array and a method of making the data storage device are described. The resistive cross point memory cell array enables high-density fabrication and high-speed operation with isolation diodes that have practical dimensions and current density characteristics. In addition, the data storage device includes a novel equipotential isolation circuit that substantially avoids parasitic currents that otherwise might interfere with the sensing of the resistance state of the memory cells. In one aspect, the memory cells of the resistive cross point memory cell array are arranged into multiple groups of two or more memory cells. The memory cells of each group are connected between a respective word line and a common isolation diode that is coupled to a bit line.

6456525, Sep 24, 2002

Sep 15, 2000

09/663752

Frederick A. Perner - Palo Alto CA
Thomas C. Anthony - Sunnyvale CA

Hewlett-Packard Company - Palo Alto CA

G11C 1114

365171, 365100, 365148, 365158

A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and a resistive element connected in series with the memory element. The resistive elements substantially attenuate any sneak path currents flowing through shorted memory elements during read operations. The data storage device may be a Magnetic Random Access Memory (âMRAMâ) device.

6462388, Oct 8, 2002

Jul 26, 2001

09/912565

Frederick A. Perner - Palo Alto CA

Hewlett-Packard Company - Palo Alto CA

H01L 2976

257390, 257209, 257262

A memory array includes memory cells located at cross points of first and second conductors. The memory cells are compound structures that are capable of storing data, and of isolating the memory cells from sneak path currents. The memory cells include tunnel gate surface effect transistors having non-uniform gate oxides. The gate oxides are supported on pillar diode structures. A memory cell stores a binary state in a tunnel junction of the gate oxide. In addition, a control gate of the transistor disconnects the tunnel junction from sidewalls of the pillar, preventing current flow. The control gate therefore prevents sneak path currents through the memory cell. The isolation features in the memory cells do not require space on the substrate, allowing for a high array density. In addition, the memory cells have a low forward voltage drop, improving the readability of the memory array.

6501697, Dec 31, 2002

Oct 11, 2001

09/976304

Frederick A. Perner - Palo Alto CA
Andrew L. Van Brocklin - Corvallis OR
Peter J. Fricke - Corvallis OR

Hewlett-Packard Company - Palo Alto CA

G11C 702

365209, 365210, 365158

A sense amplifier is provided for reading data in a multiple-state memory cell of a resistive memory array in response to a read voltage applied across the sensed memory cell, including a differential amplifier having first and second input nodes. A sense circuit determines the current in the memory cell with the read voltage applied thereto and applies a sense current representative of the memory cell current to the first input node of the differential amplifier. A reference circuit has first and second resistive elements for applying a reference current to the second input node of the differential amplifier to provide a reference value against which to compare the sense current to determine the state of the memory cell. The first resistive element has a resistance representative of a first state of the memory cell, and the second resistive element has a resistance representative of a second state of the memory cell. A voltage source for applying the read voltage across the first and second resistive elements to generate a reference current by averaging the currents through the first and second resistive elements.

6564742, May 20, 2003

Aug 3, 2001

09/921145

Frederick A Perner - Palo Alto CA
Thomas Anthony - Sunnyvale CA
Manoj Bhattacharyya - Cupertino CA

Hewlett-Packard Development Company, LLP - Houston TX

G01K 1106

116216, 374160

A critical temperature warning apparatus and method to monitor the thermal history of a product such as a memory card. The apparatus comprises a critical temperature indicator, which is externally attached to a product to be monitored. The indicator indicates if the product has experienced a critical temperature. The critical temperature indicator may comprise a patterned array of wax, the wax having a melting point equal to the critical temperature. If the pattern of wax has been destroyed leaving a molten wax residue, then this indicates that the product has experienced a critical temperature. The critical temperature indicator may also include thermographic inks for indicating that a critical temperature has been experienced.

6504779, Jan 7, 2003

May 14, 2001

09/855118

Frederick A. Perner - Palo Alto CA

Hewlett-Packard Company - Palo Alto CA

G11C 702

365209, 365129, 365158

A resistive cross point memory (RXPtM) cell array device, one example of which is a magnetic random access memory (MRAM) device, includes a chip on which is formed an array of RXPtM cells, an array of sense amplifiers used in sensing resistance values of the RXPtM cells, and an input/output (I/O) controller. The I/O controller includes a calibration controller, which tests the combination of a particularly selected memory cell and a particular associated one of the array of sense amplifiers in view of then existing environmental conditions, to assure that the sense amplifier has an acceptable calibration. Data integrity of the RXPtM cell array device is assured by a method in which each operation to sense data from the device includes a calibration test, which if not passed results in the sense amplifiers being recalibrated. When proper calibration of the sense amplifies is indicated, then sensing of the data value proceeds.

6534841, Mar 18, 2003

Dec 14, 2001

10/017567

Andrew L. Van Brocklin - Corvallis OR
Kenneth J. Eldredge - Boise ID
S. Jonathan Wang - Albany OR
Frederick A Perner - Palo Alto CA
Peter Fricke - Corvallis OR

Hewlett-Packard Company - Palo Alto CA

H01L 2900

257530, 257 50, 438129

A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.