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Frederick K Chow

from South San Francisco, CA
Age ~86
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Also known as:
Frederick Kan, Fred Chow
Phone and address:
105 Livingston Pl, South San Francisco, CA 94080
(650) 871-9496
Related to:
Manuel P Garcia, 55Rene Chow, 63Julie Chow, 84Julie Chow
Connected to:
Adriana E Chow, 41Andrew A Chow, 51Angelica M Chow, 61Aurora V Chow, 77Benson Y Chow, 51Bianca A Chow, 45Bing K Chow, 71Britney M Chow, 34Camilia A Chow, 56Celina K Chow, 47

Frederick Chow Phones & Addresses

  • 105 Livingston Pl, Ssf, CA 94080 (650) 871-9496
  • 3648 Bettman Way, South San Francisco, CA 94080
  • S San Fran, CA
  • Fitzgerald, GA
  • San Mateo, CA

Education

Degree: High school graduate or higher

Emails

f***[email protected]

Resumes

Resumes

Frederick Chow Photo 1

Software Architect In A Processor Company

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Location:
San Francisco Bay Area
Industry:
Computer Software
Frederick Chow Photo 2

Frederick Chow

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Location:
105 Livingston Pl, South San Francisco, CA 94080
Industry:
Computer Hardware
Interests:
Career
Boating
Outdoors
Sweepstakes
Home Improvement
Reading
Sports
Automobiles
Home Decoration
Languages:
English
Frederick Chow Photo 3

Frederick Chow

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Location:
United States
Frederick Chow Photo 4

Frederick Chow

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Location:
United States
Frederick Chow Photo 5

Dean, Information Technology At West Valley College

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Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Frederick Chow Photo 6

Frederick Chow

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Location:
United States
Frederick Chow Photo 7

Manager At Mechanics Bank

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Location:
San Francisco Bay Area
Industry:
Banking
Frederick Chow Photo 8

Frederick Chow

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Publications

Us Patents

Method And Computer Program Product For Global Minimization Of Sign-Extension And Zero-Extension Operations

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US Patent:
6571387, May 27, 2003
Filed:
Feb 8, 2000
Appl. No.:
09/499745
Inventors:
Frederick Chow - Fremont CA
Raymond Lo - Sunnyvale CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 945
US Classification:
717156, 717151
Abstract:
A method and computer program product, within an optimizing compiler, for the global minimization of sign-extension and zero-extension operations in generated code during compilation. The method and computer program product allows, for example, 64-bit compilers targeting the Intel IA64 architecture to improve their SPECint benchmarks by reducing the number of sign-extension and zero-extension operations in the global and intra-procedural scope, thus, speeding up the execution of the compiled program.

Lower Bound Algorithm For Operation Scheduling

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US Patent:
20050138244, Jun 23, 2005
Filed:
Dec 23, 2003
Appl. No.:
10/745259
Inventors:
Frederick Chow - Fremont CA, US
International Classification:
G06F003/00
US Classification:
710052000
Abstract:
A method and program are disclosed for scheduling operations in a digital processing system. The method includes monitoring one or more operations to be scheduled, sorting the operations based on their respective deadline processing cycles for scheduling, and storing the sorted operations in a queue. The operations are scheduled by adjusting their schedule time based on the updated system resource usage.

Method, System, And Computer Program Product For Using Static Single Assignment Form As A Program Representation And A Medium For Performing Global Scalar Optimization

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US Patent:
63017040, Oct 9, 2001
Filed:
Jun 16, 1998
Appl. No.:
9/097672
Inventors:
Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Peter Dahl - Cupertino CA
Robert Kennedy - Boulder Creek CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA
Peng Tu - Union City CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 9445
US Classification:
717 9
Abstract:
A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i. e. , optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

System And Method To Efficiently Represent Aliases And Indirect Memory Operations In Static Single Assignment Form During Compilation

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US Patent:
57685967, Jun 16, 1998
Filed:
Apr 23, 1996
Appl. No.:
8/636605
Inventors:
Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 945
US Classification:
395709
Abstract:
A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a. chi. function, zero or more occurences of a. phi. function, and zero or more occurrences of a. mu. function. The. chi. function,. phi. function, and. mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version. The optimizer further converts all indirect variables of a program to SSA form, wherein the SSA form includes a plurality of virtual variable versions such that a virtual variable is assigned to an indirect variable, zero or more occurrences of a. chi. function, zero or more occurences of a. phi.

Method, System, And Computer Program Product For Extending Sparse Partial Redundancy Elimination To Support Speculative Code Motion Within An Optimizing Compiler

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US Patent:
61517062, Nov 21, 2000
Filed:
Jun 16, 1998
Appl. No.:
9/097715
Inventors:
Raymond Lo - Sunnyvale CA
Frederick Chow - Fremont CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 945
US Classification:
717 9
Abstract:
A method, system, and computer program product for performing speculative code motion within a sparse partial redundancy elimination (PRE) framework. Speculative code motion (i. e. , speculation) refers to the placement of computations by a compiler in positions in the program that results in some paths being executed more efficiently and some being executed less efficiently. A net speed-up is thus achieved when the improved paths are those executed more frequently during the program's execution. Two embodiments for performing speculative code motion within the PRE framework are presented: (1) a conservative speculation method used in the absence of profile data; and (2) a profile-driven speculation method used when profile data are available. In a preferred embodiment, the two methods may be performed within static single assignment PRE (SSAPRE) resulting in better optimized code.

System And Method To Efficiently Represent Aliases And Indirect Memory Operations In Static Single Assignment Form During Compilation

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US Patent:
61311898, Oct 10, 2000
Filed:
Nov 26, 1997
Appl. No.:
8/979939
Inventors:
Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 945
US Classification:
717 9
Abstract:
A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a. chi. function, zero or more occurences of a. phi. function, and zero or more occurrences of a. mu. function. The. chi. function,. phi. function, and. mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version. The optimizer further converts all indirect variables of a program to SSA form, wherein the SSA form includes a plurality of virtual variable versions such that a virtual variable is assigned to an indirect variable, zero or more occurrences of a. chi. function, zero or more occurences of a. phi.

Method, System, And Computer Program Product For Performing Register Promotion Via Load And Store Placement Optimization Within An Optimizing Compiler

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US Patent:
6128775, Oct 3, 2000
Filed:
Jun 16, 1998
Appl. No.:
9/097713
Inventors:
Frederick Chow - Fremont CA
Robert Kennedy - Boulder Creek CA
Raymond Lo - Sunnyvale CA
Peng Tu - Union City CA
Sun C. Chan - Fremont CA
Assignee:
Silicon Graphics, Incorporated - Mountain View CA
International Classification:
G06F 945
US Classification:
717 9
Abstract:
A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results. A static single use (SSU) representation is defined allowing the dual of the SSAPRE algorithm, called SSUPRE, to perform the partial redundancy elimination of stores. SSUPRE is performed after the PRE of loads, taking advantage of the loads' having been converted into pseudo-register references so that there are fewer barriers to the movement of stores.

System And Method For Optimizing A Source Code Representation As A Function Of Resource Utilization

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US Patent:
57349088, Mar 31, 1998
Filed:
May 31, 1995
Appl. No.:
8/455238
Inventors:
Sun C. Chan - Fremont CA
Frederick Chow - Fremont CA
Raymond W. Lo - Sunnyvale CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 945
US Classification:
395709
Abstract:
A system and method for optimizing a source code representation comprising a plurality of basic blocks are described. The optimized source code representation is to be executed in a target machine. The system operates by selecting from the source code representation a basic block pair comprising a source basic block and one or more target basic blocks. An instruction in the source basic block is identified that can be moved from the source basic block to the target basic block(s) while preserving program semantics. Either the instruction or a representation of the instruction is moved from the source basic block to the target basic block(s) as a function of resource utilization of the target machine that would result from this movement.
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Frederick K Chow from South San Francisco, CA, age ~86 Get Report