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Frederic Nicolas Deboes

from Austin, TX
Age ~60

Frederic Deboes Phones & Addresses

  • 4424 Lago Viento, Austin, TX 78734 (512) 266-3251
  • Dallas, TX
  • 20693 Garden Manor Ct, Cupertino, CA 95014
  • Burlington, MA
  • San Jose, CA

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Graduate or professional degree

Resumes

Resumes

Frederic Deboes Photo 1

Manager, Analog Design

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Microchip Technology
Manager, Analog Design

Pulsewave Rf 2006 - 2008
Principal Staff Engineer

Vitesse Semiconductor 2005 - 2006
Design Manager

Lattice Semiconductor 2001 - 2005
Design Manager

Quantum 1995 - 2001
Design Manager
Education:
Caltech 1986 - 1987
Masters, Electrical Engineering
Esiee Paris 1982 - 1987
Skills:
Ic
Mixed Signal
Analog
Cmos
Semiconductors
Analog Circuit Design
Integrated Circuit Design
Bicmos
Circuit Design
Phy
Pll
Serdes
Power Management
Servo Control
Physical Design
Adcs
Oscillators
Power Electronics Design
Control Theory
Numerical Simulation
Monte Carlo Simulation
Debugging
Validation
Languages:
English
French
German
Frederic Deboes Photo 2

Frederic Deboes

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Publications

Us Patents

Analog-To-Digital Systems And Methods

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US Patent:
7630464, Dec 8, 2009
Filed:
Apr 19, 2005
Appl. No.:
11/109301
Inventors:
Frederic Deboes - Austin TX, US
John Pacourek - Austin TX, US
Tom Cook - Austin TX, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03D 1/04
H03M 1/06
H03M 1/12
US Classification:
375346, 341118, 341155
Abstract:
Systems and methods are disclosed herein to provide analog-to-digital interface techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an offset cancellation circuit provides offset cancellation for input signal paths under control of at least a first clock signal. A comparator, coupled to the offset cancellation circuit, provides an output signal based on a comparison of input signals provided on the input signal paths. A register receives the output signal and provides the output signal to a digital circuit under control of a first control signal, wherein the at least first clock signal is synchronized to a clock signal of the digital circuit.

Power Supply Control Circuits

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US Patent:
20040070998, Apr 15, 2004
Filed:
Oct 10, 2002
Appl. No.:
10/269450
Inventors:
Frederic Deboes - Austin TX, US
Ludmil Nikolov - Chippenham, GB
Hans Klein - Danville CA, US
Geoffrey Rickard - Cirencester, GB
International Classification:
H02M003/315
US Classification:
363/028000
Abstract:
Power supply sequencing systems and methods are disclosed. In one embodiment, a programmable charge pump supplies a programmable current source, which drives an external NFET that controls whether power is supplied to a device or a portion of circuitry. The maximum voltage and the turn-on ramp rate supplied to the NFET are programmable and, therefore, the NFET can be operated safely within its rated limits without requiring external protection devices. If a high-voltage output terminal is not required to drive an external NFET, the output terminal, in accordance with another embodiment, may be configured to function as an open drain logic output terminal.

Low Pass Filter Systems And Methods

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US Patent:
6998906, Feb 14, 2006
Filed:
Apr 29, 2004
Appl. No.:
10/834528
Inventors:
Thomas Cook - Austin TX, US
Frederic Deboes - Austin TX, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H01K 5/00
US Classification:
327558, 327 34, 327551, 708300
Abstract:
Systems and methods are disclosed herein to provide low pass filters. For example, in accordance with an embodiment of the present invention, a synchronous low pass filter is disclosed. The filter may be employed, for example, to suppress signal transients in power supply monitoring applications.
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