Frank R Prein

6335228, Jan 1, 2002

Dec 30, 1999

09/476726

Robert T. Fuller - Mechanicsville VA
Frank Prein - Glen Allen VA

Infineon Technologies North America Corp. - Cupertino CA
White Oak Semiconductor Partnership - Sandstone VA

H01L 2182

438131, 438600

A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i. e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact ( ) and a normal (i. e. non-fused) contact ( ) are formed by opening respective contact areas in a dielectric ( ), selectively forming an insulating layer ( ) over the anti-fuse contact, applying polysilicon ( ) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation ( ) to improve its conductivity before the anti-fuse contact is formed. In another embodiment of the invention, the anti-fuse is formed in an isolated well ( ) on the integrated circuit device and a non-fused contact ( ) to the well is also provided to aid in blowing the anti-fuse.

59171979, Jun 29, 1999

May 21, 1997

8/861465

Frank Alswede - Wappingers Falls NY
William Davies - Pleasant Valley NY
Ronald Hoyer - Poughkeepsie NY
Ron Mendelson - Richmond VT
Frank Prein - Wappingers Falls NY

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

H01L 2358

257 48

A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3. times. 3 block of the first pads.

58997067, May 4, 1999

Jun 30, 1997

8/884862

Andreas Kluwe - Essex Junction VT
Lars Liebmann - Poughquag NY
Frank Prein - Glen Allen VA
Thomas Zell - Dresden, DE

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

H01L 2182

438129

In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

61210749, Sep 19, 2000

Nov 5, 1998

9/186515

Frank Prein - Glen Allen VA

Siemens Aktiengesellschaft - Munich

H01L 2182

438132

A method of fabricating a fuse for a semiconductor memory, in accordance with the invention, includes the steps of forming a gate structure on a substrate including a polysilicon fuse layer and a gate cap layer disposed above the polysilicon fuse layer, forming an interlevel dielectric layer over the gate structure, depositing a dielectric layer over the interlevel dielectric layer, the dielectric layer and the interlevel dielectric layer both including a material which is selectively etchable relative to the gate cap layer and selectively etching contact holes through the dielectric layer and the interlevel dielectric layer such that at least one contact hole is formed over the gate structure and extends into the gate cap layer.

56082576, Mar 4, 1997

Jun 7, 1995

8/477060

Frank Prein - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 2710
H01L 2900

257529

In an integrated circuit having interconnecting lines formed on an insulated layer deposited on a semiconductor substrate which provide connections between elements integral to the integrated circuit, a fuse structure programmable by a laser beam that includes: a melt-away elongated fuse link joining two segments of an interconnecting line; a plurality of fins integral and coplanar to the fuse link, each of the fins transversally extending away from the fuse link for absorbing energy emitted by the laser beam; and a reflecting plate positioned underneath the fuse link to reflect energy provided by the laser beam back into the fuse link, such that both the combination of the fins and the reflecting plate reduces the energy emitted by the laser beam required to blow the fuse structure.

61747416, Jan 16, 2001

Dec 19, 1997

8/994273

Wilfried Hansch - Midlothian VA
Frank Prein - Glen Allen VA
Jurgen Faul - Radebeul, DE

Siemens Aktiengesellschaft - Munich

G01R 3126
H01L 2166

438 14

Improved techniques for quantifying proximity effects during fabrication of integrated circuits are disclosed. The improved techniques use active features formed on a semiconductor wafer to quantify proximity effects. According to the improved techniques, a device performance quantity for an active feature is measured, and then a feature length for the active feature is determined in accordance with the measured device performance quantity. The fabrication processing can then be evaluated and/or compensated based on the determined feature length. In one example, the active feature can be a metal-oxide semiconductor (MOS) transistor and the device performance quantity can be current.

60700041, May 30, 2000

Sep 25, 1997

8/937764

Frank Prein - Glen Allen VA

Siemens Aktiengesellschaft - Munich

G06F 1750
G06F 1900
G06K 903

39550011

A method of fabricating semiconductor chips includes the steps of optimizing a number of chips that geometrically fit on a wafer and maximizing chip yield for the wafer by considering chips located in a normally rejectable location and utilizing yield probability data for the chip in the normally rejectable locations to weight the probability of an acceptable chip such that if the probability is above a threshold value the chips are not rejected. This results in an increased chip yield for semiconductor wafers.

59813024, Nov 9, 1999

Feb 23, 1999

9/256048

Frank Alswede - Wappingers Falls NY
William Davies - Pleasant Valley NY
Ronald Hoyer - Poughkeepsie NY
Ron Mendelson - Richmond VT
Frank Prein - Wappingers Falls NY

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

H01L 2144

438 15

A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3. times. 3 block of the first pads.