Search

Frank William Liljeros

from Sanford, FL
Age ~51
Get Report
Also known as:
Frank W Liljeros, William F Liljeros, Frank S
Phone and address:
320 Kimberly Ct, Sanford, FL 32771
(407) 895-9150
Related to:
Lydia Bell, 62Anita Liljeros
Connected to:
Bonnie L Liljestrand, 73Ingram J Liljestrand, 56Karin Liljestrand, 54Jeanine M Lilke, 38Ian Lilkendey, 45Carrie F Lill, 46Jeffrey P Lill, 67Justin J Lill, 39Kaela T Lill, 36Rosann T Lill, 78

Frank Liljeros Phones & Addresses

  • 320 Kimberly Ct, Sanford, FL 32771 (407) 895-9150
  • 178 Brushcreek Dr, Sanford, FL 32771 (407) 328-4739
  • 517 Kays Landing Dr, Sanford, FL 32771 (407) 328-4739
  • Black Mountain, NC
  • 3224 Tidal Pool Cv, Lake Mary, FL 32746
  • 1929 Osman Ave, Orlando, FL 32806 (407) 895-9150
  • 3200 Arden Villas Blvd, Orlando, FL 32817 (407) 736-0463
  • 3900 17Th St, Ocala, FL 34480 (352) 629-8855
  • Seminole, FL
  • 320 Kimberly Ct, Sanford, FL 32771 (407) 463-4712

Work

Company: Apple Jan 2013 Position: Graphics hardware engineer

Education

Degree: MSEE School / High School: University of Florida 1998 to 1999 Specialities: Computer Engineering

Skills

Asic • Rtl Design • Verilog • Processors • Soc • Gpu • Computer Architecture • Static Timing Analysis • Debugging • Hardware Architecture • Timing Closure • Functional Verification • Systemverilog • Logic Design • Microarchitecture • Rtl Coding • Vlsi • Simulations • Microprocessors • Logic Synthesis

Industries

Computer Hardware

Resumes

Resumes

Frank Liljeros Photo 1

Graphics Hardware Engineer @ Apple

View page
Location:
320 Kimberly Ct, Sanford, FL 32771
Industry:
Computer Hardware
Work:
Apple since Jan 2013
Graphics Hardware Engineer
Advanced Micro Devices Jan 2000 - Jan 2013
ASIC Design - SMTS
Education:
University of Florida 1998 - 1999
MSEE, Computer Engineering
Skills:
Asic
Rtl Design
Verilog
Processors
Soc
Gpu
Computer Architecture
Static Timing Analysis
Debugging
Hardware Architecture
Timing Closure
Functional Verification
Systemverilog
Logic Design
Microarchitecture
Rtl Coding
Vlsi
Simulations
Microprocessors
Logic Synthesis

Business Records

Name / Title
Company / Classification
Phones & Addresses
Frank Liljeros
Chairman, Secretary
Presbyterian Church In America (A Corporation)
Religious Organization · Churches
405 Washington Ave, Lake Mary, FL 32746
385 Washington Ave, Lake Mary, FL 32746
(407) 330-9103, (407) 330-7456

Publications

Us Patents

Hardware-Based Scheduling Of Gpu Work

View page
US Patent:
8310492, Nov 13, 2012
Filed:
Sep 3, 2009
Appl. No.:
12/553637
Inventors:
Rex McCrary - Ouiedo FL, US
Frank Liljeros - Sanford FL, US
Gongxian Jefferey Cheng - Toronto, CA
Assignee:
ATI Technologies ULC - Markham, Ontario
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06T 1/00
G06T 1/20
G06F 9/46
US Classification:
345522, 345506, 718102, 718103, 718104, 718105
Abstract:
An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.

Course Grain Command Buffer

View page
US Patent:
20110063311, Mar 17, 2011
Filed:
Sep 9, 2010
Appl. No.:
12/878519
Inventors:
Rex McCRARY - Oviedo FL, US
Frank LILJEROS - Sanford FL, US
Gongxian Jeffrey CHENG - Toronto, CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06T 15/00
G06F 3/00
US Classification:
345522, 710 52
Abstract:
A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

On-Demand Memory Allocation

View page
US Patent:
20210271606, Sep 2, 2021
Filed:
Feb 28, 2020
Appl. No.:
16/804128
Inventors:
- Cupertino CA, US
Karl D. Mann - Geneva FL, US
Yoong Chert Foo - London, GB
Terence M. Potter - Austin TX, US
Frank W. Liljeros - Sanford FL, US
Ralph C. Taylor - Deland FL, US
International Classification:
G06F 12/1018
G06F 12/084
Abstract:
Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

Cache Memory With Transient Storage For Cache Lines

View page
US Patent:
20210055883, Feb 25, 2021
Filed:
Aug 22, 2019
Appl. No.:
16/548784
Inventors:
- Cupertino CA, US
Sindhuja Sethuraman - Orlando FL, US
Frank W. Liljeros - Sanford FL, US
Adil M. Sadik - Orlando FL, US
International Classification:
G06F 3/06
G06F 12/0871
Abstract:
Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.
Control profile
Frank William Liljeros from Sanford, FL, age ~51 Get Report