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Frank T Hady

from Portland, OR
Age ~60
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Also known as:
Frank Thomas Hady, Thomas F Hady
Phone and address:
12888 Lorraine Dr, Portland, OR 97229
(503) 690-8182
Related to:
Ryan F Kirkland, 44Jeremy Marquis Freeman, 51Thomas Hady, 92Thomas F Hady, 30Joan Hady, 26Alice HadyThomas Hady
Connected to:
Brian T Hady, 41Clyde J Hady, 69James A Hady, 93John J Hady, 35Daniela V Hadzhieva, 44Diana M Hadzhieva, 36Petar Hadzhiev, 42Cristina Hadzi, 68Eldin Hadziabdic, 52Habiba Hadziavdic, 49

Frank Hady Phones & Addresses

  • 12888 Lorraine Dr, Portland, OR 97229 (503) 690-8182
  • 1782 Caitlin Ter, Portland, OR 97229 (503) 644-4514 (503) 690-8182
  • Cannon Beach, OR
  • Burtonsville, MD
  • Springfield, VA
  • Laurel, MD
  • Hillsboro, OR
  • 12888 NW Lorraine Dr, Portland, OR 97229 (503) 644-4514

Work

Position: Protective Service Occupations

Resumes

Resumes

Frank Hady Photo 1

Intel Fellow And Director Of Storage Technology Group

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Location:
12888 northwest Lorraine Dr, Portland, OR 97229
Industry:
Semiconductors
Work:
Intel Corporation
Intel Fellow and Director of Storage Technology Group
Intel Corporation Jan 2010 - Aug 2016
Intel Fellow, Chief Architect For Optane Ssds and Memory
Intel Corporation Apr 1995 - Jan 2010
Staff To Principal Engineer, Platform Researcher
Supercomputing Research Center 1989 - 1995
Researcher
Education:
University of Maryland College Park 1989 - 1993
PhD, Electrical Engineering University of Virginia 1983 - 1989
BS & MS, EE
Skills:
Memory
Intel
Technology
Research
Manufacturing
Platform
Platform Architecture
Frank Hady Photo 2

Frank Hady

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Publications

Us Patents

Method And System For Simultaneously Displaying The Throughput On Multiple Busses

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US Patent:
6437783, Aug 20, 2002
Filed:
Sep 13, 1999
Appl. No.:
09/394993
Inventors:
Anthony S. Bock - Vancouver WA
Mason B. Cabot - Portland OR
Rick L. Coulson - Portland OR
Frank T. Hady - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 1120
US Classification:
345440, 702182, 714 39
Abstract:
A method and system are disclosed for measuring simultaneously and at randomly distributed intervals throughputs sets on one or more busses under test and displaying the percent occurrences of those throughputs sets in a graph as a density function. A method and system are also disclosed for simultaneously measuring throughput sets on one or more busses under test given that user specified stimuli are input into those busses and displaying those throughput sets in a graph as concurrency plots.

Apparatus, Method And System For Determining Application Runtimes Based On Histogram Or Distribution Information

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US Patent:
6564175, May 13, 2003
Filed:
Mar 31, 2000
Appl. No.:
09/540481
Inventors:
Frank T. Hady - Portland OR
Mason Cabot - San Francisco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1134
US Classification:
702186, 702187, 702178, 702179, 717124, 717127, 717131, 714 38, 713500
Abstract:
A method for determining an estimated runtime of a software application, the method including the providing of a reference runtime of the software application for a reference system configuration, wherein the reference system configuration includes a processor, a processor bus and at least one processor service component, the providing of a processor bus utilization parameter associated with the reference system configuration, the providing of a first processor bus queue statistic associated with the reference runtime, the providing of a second processor bus queue statistic associated with the reference runtime, and determining the estimated runtime based on the reference runtime, the processor bus utilization parameter, the first processor bus queue statistic and the second processor bus queue statistic.

Apparatus, Method And System For Counting Logic Events, Determining Logic Event Histograms And For Identifying A Logic Event In A Logic Environment

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US Patent:
6647349, Nov 11, 2003
Filed:
Mar 31, 2000
Appl. No.:
09/539940
Inventors:
Frank T. Hady - Portland OR
Brad W Hosler - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1134
US Classification:
702 89
Abstract:
A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

System For Dynamically Configuring System Logic Device Coupled To The Microprocessor To Optimize Application Performance By Reading From Selection Table Located In Non-Volatile Memory

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US Patent:
6687821, Feb 3, 2004
Filed:
Mar 31, 2000
Appl. No.:
09/541381
Inventors:
Frank T. Hady - Portland OR
Mason B. Cabot - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
713100, 710113, 710116, 712 43
Abstract:
An example embodiment of a method and apparatus for dynamically changing computer system configuration to improve software application performance includes a system logic device that implements at least two different configurations. The system logic device may change configuration depending on what software application is running. The system logic device can change configurations while the computer system is running and may change configurations in order to optimize performance for whatever application is currently running.

Apparatus, Method And System For Counting Logic Events, Determining Logic Event Histograms And For Identifying A Logic Event In A Logic Environment

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US Patent:
6856944, Feb 15, 2005
Filed:
Sep 17, 2003
Appl. No.:
10/666968
Inventors:
Frank T. Hady - Portland OR, US
Brad W Hosler - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F003/05
US Classification:
702188, 702182, 702183, 702186
Abstract:
A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

Method And Apparatus For Gathering Queue Performance Data

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US Patent:
6950887, Sep 27, 2005
Filed:
May 4, 2001
Appl. No.:
09/848998
Inventors:
James S. Chapple - Chandler AZ, US
Kalpesh D. Mehta - Chandler AZ, US
Frank T. Hady - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F003/00
US Classification:
710 55, 710 23, 710 39, 710 52, 711156, 370232, 370413
Abstract:
An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Integrated Circuit With Trace Analyzer

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US Patent:
7079490, Jul 18, 2006
Filed:
Dec 3, 1998
Appl. No.:
09/204257
Inventors:
Frank Hady - Portland OR, US
Rick Coulson - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/26
G06F 11/00
G01R 31/28
US Classification:
370241, 370402, 370463, 714 30, 714742
Abstract:
An integrated circuit includes a trace analyzer to sample, process and store data carried along internal or external data path of the circuit. The trace analyzer may include a multiplexer, a sampler, a formatter and a memory controller. The trace analyzer samples data on a predetermined basis, processes it and caused the processed data to be stored in a memory.

Method Of Implementing Off-Chip Cache Memory In Dual-Use Sram Memory For Network Processors

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US Patent:
7200713, Apr 3, 2007
Filed:
Mar 29, 2004
Appl. No.:
10/811608
Inventors:
Mason B. Cabot - San Francisco CA, US
Frank T. Hady - Portland OR, US
Mark B. Rosenbluth - Uxbridge MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711108, 711148, 711153, 711173
Abstract:
A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i. e. , conventional SRAM use). The cache region is used to store cached data corresponding to portions of data contained in a second off-chip memory store, such as a dynamic RAM (DRAM) memory store or an alternative type of memory store, such as a Rambus DRAM (RDRAM) memory store. An on-chip cache management controller is integrated on the network processor. Various cache management schemes are disclosed, including hardware-based cache tag arrays, memory-based cache tag arrays, content-addressable memory (CAM)-based cache management, and memory address-to-cache line lookup schemes. Under one scheme, multiple network processors are enabled to access shared SRAM and shared DRAM, wherein a portion of the shared SRAM is used as a cache for the shared DRAM.
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Frank T Hady from Portland, OR, age ~60 Get Report