Resumes
Resumes
Project Manager
View pageWork:
Walmart
Project Manager
Project Manager
Frank Cartman Phones & Addresses
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Pawling, NY
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3 Jack And Jill Rd, Poughquag, NY 12570 (845) 724-5766
Work
Company:
Walmart
Position:
Project manager
Publications
Us Patents
Memory Access System Including A Memory Controller With Memory Redrive Circuitry
View pageUS Patent:
54796407, Dec 26, 1995
Filed:
Jun 30, 1993
Appl. No.:
8/085215
Inventors:
Frank P. Cartman - Poughquag NY
Brian W. Curran - Saugerties NY
Matthew A. Krygowski - Hopewell Junction NY
Tin-Chee Lo - Fishkill NY
Sandy N. Luu - Wappingers Falls NY
Sanjay B. Patel - Cary NC
William W. Shen - Poughkeepsie NY
Brian W. Curran - Saugerties NY
Matthew A. Krygowski - Hopewell Junction NY
Tin-Chee Lo - Fishkill NY
Sandy N. Luu - Wappingers Falls NY
Sanjay B. Patel - Cary NC
William W. Shen - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1202
US Classification:
395438
Abstract:
A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.
Multi-Bit Error Scattering Arrangement To Provide Fault Tolerant Semiconductor Static Memories
View pageUS Patent:
44882980, Dec 11, 1984
Filed:
Jun 16, 1982
Appl. No.:
6/388834
Inventors:
George L. Bond - Fishkill NY
Frank P. Cartman - Poughquag NY
Philip M. Ryan - Hopewell Junction NY
Frank P. Cartman - Poughquag NY
Philip M. Ryan - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1110
US Classification:
371 11
Abstract:
A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n. times. m) of separate memory chips arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n (16) word m (72) bit position buffer during a memory read operation. Steering logic responsive to control signals is disposed between the memory and the buffer which permits the n chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location.