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Fong Nam Lin

from Bay Point, CA
Age ~82
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Also known as:
Fong Mei-Tso Lin, Fong N Lin, Fong Mei Lin, Nam Fong Lin, Nam Lin Fong, Fongnam Lin, Fong Mei Tso, Lin Nam Fongnam, Lin Fong
Phone and address:
2986 Pilar Ridge Dr, West Pittsburg, CA 94565
Related to:
Melody L Moravec, 63Yu S Chen, 69Chien C Chen, 87Yuchun Chun Lin, 51Carolyn Hung LinChinghua Hua LinMuchen C Lu, 65Hsiu Chen, 63Stephanie H Chen, 46Jennifer Y Chen, 49Yuche Lin, 50Iyin Yin Chen, 50Chiulin HoYuchun Chun Linyu, 51Yue Chan, 65Chen Shun Joe, 80Hsiu C Chen, 64Hunglin Jung Carolyn, 83Tina Chen, 52Anothai Tanadumrongsak, 48
Connected to:
Abbie Lin, 37Adie S Lin, 80Adora A Lin, 44Agnes C Lin, 46Aileen Lin, 55Alston C Lin, 27Angela L Lin, 75Angelo C Lin, 60Anne Lin, 45Anya Y Lin, 47

Fong Lin Phones & Addresses

  • 2986 Pilar Ridge Dr, Pittsburg, CA 94565
  • Bay Point, CA
  • 3352 Ashbourne Cir, San Ramon, CA 94583
  • Concord, CA
  • Piedmont, CA
  • Alameda, CA
  • Walnut, CA
  • Bethesda, MD
  • Walnut Creek, CA

Professional Records

Lawyers & Attorneys

Fong Lin Photo 1

Fong Lin - Lawyer

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ISLN:
1000537578
Admitted:
1981

Publications

Us Patents

Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die

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US Patent:
7851273, Dec 14, 2010
Filed:
Apr 19, 2010
Appl. No.:
12/762825
Inventors:
Kangping Zhang - Fremont CA, US
Fong Long Lin - Fremont CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L 21/82
H01L 27/10
US Classification:
438129, 257203
Abstract:
In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Memory Controller And A Method Of Operating An Electrically Alterable Non-Volatile Memory Device

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US Patent:
20100138588, Jun 3, 2010
Filed:
Dec 2, 2008
Appl. No.:
12/326811
Inventors:
Fong Long Lin - Fremont CA, US
Je-Hurn Shieh - Cupertino CA, US
International Classification:
G06F 12/02
G06F 12/00
US Classification:
711103, 711E12001, 711E12008
Abstract:
A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.
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Fong Nam Lin from Bay Point, CA, age ~82 Get Report