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Fenardi S Thenus

from Portland, OR
Age ~51
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Also known as:
Fernardi Thenus
Phone and address:
15446 NW Andalusian Way, Portland, OR 97229
(503) 466-2577
Related to:
Susanny R Thenus, 50Susanny R Thenus, 80Susanny Mulyadi, 50
Connected to:
Angelo Theo, 49Charles O Theo, 70Donald G Theo, 74Jim J Theo, 101Joseph J Theo, 32Philip P Theo, 59Teddy Theo, 73Andrew G Theobald, 62Ashley A Theobald, 35Brian Theobalds, 40

Fenardi Thenus Phones & Addresses

  • 15446 NW Andalusian Way, Portland, OR 97229 (503) 466-2577
  • 3341 NW 154Th Ter, Portland, OR 97229 (503) 466-2577
  • 970 SW 163Rd Ave #716, Beaverton, OR 97006
  • Hillsboro, OR
  • 145 NW 16Th St #102, Corvallis, OR 97330 (541) 758-7401
  • 3341 NW 154Th Ter, Portland, OR 97229

Work

Company: Intel corporation Jul 2015 Position: Senior analog design engineer

Education

Degree: Masters School / High School: Oregon State University 1996 to 1998

Skills

Mixed Signal • Analog Circuit Design • Asic • Ic • Debugging • Verilog • Cmos • Analog • Semiconductors • Vlsi • Circuit Design • Fpga • Soc • Electronics • Embedded Systems • C • Integrated Circuit Design • Integrated Circuits

Industries

Electrical/Electronic Manufacturing

Public records

Vehicle Records

Fenardi Thenus

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Address:
3341 NW 154 Ter, Portland, OR 97229
Phone:
(503) 466-2577
VIN:
WBAWB73507P022809
Make:
BMW
Model:
3 SERIES
Year:
2007

Resumes

Resumes

Fenardi Thenus Photo 1

Senior Analog Design Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Electrical/Electronic Manufacturing
Work:
Intel Corporation
Senior Analog Design Engineer
Intel Corporation Mar 2004 - Mar 2015
Analog Design Engineer
Intel Corporation Mar 2004 - Mar 2015
Component Design Engineer
Network Elements Mar 2002 - 2004
Mixed Signal Design Engineer
Triquint Semiconductor 1998 - 2002
Design Engineer
Education:
Oregon State University 1996 - 1998
Masters Oregon State University 1993 - 1996
Bachelors
Skills:
Mixed Signal
Analog Circuit Design
Asic
Ic
Debugging
Verilog
Cmos
Analog
Semiconductors
Vlsi
Circuit Design
Fpga
Soc
Electronics
Embedded Systems
C
Integrated Circuit Design
Integrated Circuits

Business Records

Name / Title
Company / Classification
Phones & Addresses
Fenardi Thenus
Principal
Xceed Vision LLC
Nonclassifiable Establishments
5513 NW Bannister Dr, Portland, OR 97229

Publications

Us Patents

Second Order Continuous Time Linear Equalizer

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US Patent:
20080101450, May 1, 2008
Filed:
Oct 26, 2006
Appl. No.:
11/586920
Inventors:
Zuoguo Wu - Santa Clara CA, US
Peng Zou - Northborough MA, US
Fenardi Thenus - Portland OR, US
International Classification:
H03K 5/159
US Classification:
375232
Abstract:
According to some embodiments, a continuous time linear equalization circuit includes an input of a first stage to receive a differential input signal, and an output of the first stage to output a differential output signal. A transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and the differential output signal is not fed back to the first stage.

Frequency Multiplying Delay-Locked Loop

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US Patent:
20080116951, May 22, 2008
Filed:
Nov 22, 2006
Appl. No.:
11/603531
Inventors:
Zuoguo Wu - Santa Clara CA, US
Fenardi Thenus - Portland OR, US
Sanjay Dabral - Palo Alto CA, US
International Classification:
H03L 7/00
US Classification:
327161
Abstract:
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated which have increased frequency relative to the incoming signal.

Method And Apparatus For Power Profile Shaping Using Time-Interleaved Voltage Modulation

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US Patent:
20110154071, Jun 23, 2011
Filed:
Dec 18, 2009
Appl. No.:
12/641916
Inventors:
Peng Zou - Tumwater WA, US
Fenardi Thenus - Portland OR, US
International Classification:
G06F 1/32
US Classification:
713320
Abstract:
Embodiments of an apparatus, system and method are described for dynamically time-interleaving supply voltage modulation to shape a power profile. An apparatus may comprise, for example, a power management module to monitor power information received from a plurality of devices and send a power control signal including delay information to each device having power information that exceeds a power threshold, the delay information comprising information for time-interleaving power usage among the devices having power information that exceeds the power threshold. Other embodiments are described and claimed.

Interface Circuitry For A Test Apparatus

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US Patent:
20140070846, Mar 13, 2014
Filed:
Sep 13, 2012
Appl. No.:
13/613810
Inventors:
Peng Zou - Tumwater WA, US
Fenardi Thenus - Portland OR, US
David J. Harriman - Portland OR, US
International Classification:
H03K 19/0175
US Classification:
326 82
Abstract:
In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.

Apparatus For Starting Up Switching Voltage Regulator

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US Patent:
20160315532, Oct 27, 2016
Filed:
May 11, 2016
Appl. No.:
15/152456
Inventors:
- Santa Clara CA, US
Fenardi Thenus - Portland OR, US
Peng Zou - Portland OR, US
Henry W. Koertzen - Olympia WA, US
International Classification:
H02M 1/36
H02M 3/158
Abstract:
Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Low Power High Frequency Digital Pulse Frequency Modulator

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US Patent:
20160111061, Apr 21, 2016
Filed:
Jun 10, 2013
Appl. No.:
14/129269
Inventors:
Fenardi THENUS - Portland OR, US
Peng ZOU - Portland OR, US
Raghu Nandan CHEPURI - Bangalore, IN
Henry K. KOERTZEN - Olympia WA, US
International Classification:
G09G 5/00
H03K 17/284
G06F 3/041
H03K 7/06
H02M 3/158
H03K 5/14
H03K 7/08
Abstract:
Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.

Apparatus For Starting Up Switching Voltage Regulator

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US Patent:
20140250310, Sep 4, 2014
Filed:
Mar 1, 2013
Appl. No.:
13/783115
Inventors:
Raghu Nandan CHEPURI - Bangalore, IN
Fenardi THENUS - Portland OR, US
Peng ZOU - Tumwater WA, US
Henry W. KOERTZEN - Olympia WA, US
International Classification:
G05F 1/10
G06F 1/26
US Classification:
713300, 323282
Abstract:
Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Method And Apparatus Of Current Balancing For Multiple Phase Power Converter

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US Patent:
20140167711, Jun 19, 2014
Filed:
Dec 19, 2012
Appl. No.:
13/720050
Inventors:
Fenardi Thenus - Portland OR, US
Peng Zou - Tumwater WA, US
International Classification:
G05F 1/46
US Classification:
323234
Abstract:
In some embodiments described herein, proposed schemes utilize a duty-cycle sensing technique to detect load current imbalance in each individual inductor, and then adjusts the duty cycles for the specific phases through a digital duty cycle tuner.
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Fenardi S Thenus from Portland, OR, age ~51 Get Report