Farid Abooameri

20020075631, Jun 20, 2002

Dec 27, 2000

09/749262

Kaushal Singh - Santa Clara CA, US
Farid Abooameri - Santa Clara CA, US
Visweswaren Sivaramakrishnan - Santa Clara CA, US
Talex Sajoto - San Jose CA, US
Vicente Lim - Newark CA, US
Jun Zhao - Cupertino CA, US

Applied Materials, Inc.

H01G004/06

361/311000

The present invention provides a capacitor having upper and lower electrodes formed of iridium or iridium oxide or combinations thereof. The electrodes are preferably formed using physical vapor deposition. An insulating layer disposed between the electrodes can be a ferroelectric ceramic such as PZT or PLZT.

20040018739, Jan 29, 2004

Jul 26, 2002

10/206252

Farid Abooameri - Pleasanton CA, US
Shashank Deshmukh - San Jose CA, US
Meihua Shen - Fremont CA, US
Stephanie Cheng - San Francisco CA, US
Nicolas Gani - Milpitas CA, US
Thorsten Lill - Santa Clara CA, US

Applied Materials, Inc.

H01L021/302
H01L021/461

438/709000

One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.

20040152331, Aug 5, 2004

Sep 11, 2003

10/660151

Songlin Xu - Fremont CA, US
Thorsten Lill - Santa Clara CA, US
Yeajer Chen - Fremont CA, US
Mohit Jain - San Jose CA, US
Nicolas Gani - Milpitas CA, US
Shing-Li Sung - Hsin-Chu, TW
Jitske Kretz - San Jose CA, US
Meihua Shen - Fremont CA, US
Farid Abooameri - Pleasanton CA, US

Applied Materials, Inc.

H01L021/3205
H01L021/4763

438/719000

The present invention provides a process of etching polysilicon gates using a silicon dioxide hard mask. The process includes exposing a substrate with a polysilicon layer formed thereon to a plasma of a process gas, which includes a base gas and an additive gas. The base gas includes HBr, Cl, O, and the additive gas is NFand/or N. By changing a volumetric flow ratio of the additive gas to the base gas, the etch rate selectivity of polysilicon to silicon dioxide may be increased, which allows for a thinner hard mask, better protection of the gate oxide layer, and better endpoint definition and control. Additionally, when the polysilicon layer includes both N-doped and P-doped regions, the additive gas includes both NFand N, and by changing a volumetric flow ratio of NFto N, the etching process may be tailored to provide optimal results in N/P loading and microloading.

20070256785, Nov 8, 2007

May 3, 2006

11/381523

Sharma Pamarthy - Hayward CA, US
Huutri Dao - San Jose CA, US
Xiaoping Zhou - San Jose CA, US
Kelly McDonough - San Jose CA, US
Jivko Dinev - Cupertino CA, US
Farid Abooameri - San Ramon CA, US
David Gutierrez - San Jose CA, US
Jim He - Sunnyvale CA, US
Robert Clark - San Jose CA, US
Dennis Koosau - Hayward CA, US
Jeffrey Dietz - San Jose CA, US
Declan Scanlan - Sunnyvale CA, US
Subhash Deshmukh - San Jose CA, US
John Holland - San Jose CA, US
Alexander Paterson - San Jose CA, US

H01L 21/306
H01L 21/302

156345330, 156345240, 438689000

Embodiments of the invention provide a method and apparatus, such as a processing chamber, suitable for etching high aspect ratio features. Other embodiments include a showerhead assembly for use in the processing chamber. In one embodiment, a processing chamber includes a chamber body having a showerhead assembly and substrate support disposed therein. The showerhead assembly includes at least two fluidly isolated plenums, a region transmissive to an optical metrology signal, and a plurality of gas passages formed through the showerhead assembly fluidly coupling the plenums to the interior volume of the chamber body.

20100099266, Apr 22, 2010

Sep 21, 2009

12/563526

Manfred Oswald - Tharandt, DE
Jivko Dinev - Santa Clara CA, US
Jan Rupf - Dresden, DE
Markus Meye - Dresden, DE
Francesco Maletta - Radebeul, IT
Uwe Leucke - Dresden, DE
Ron Tilger - Dresden, DE
Farid Abooameri - Pleasanton CA, US
Alexander Matyushkin - San Jose CA, US
Denis Koosau - Hayward CA, US
Xiaoping Zhou - San Jose CA, US
Thorsten Lehmann - Dohna, DE
Declan Scanlan - Sunnyvale CA, US

APPLIED MATERIALS, INC. - Santa Clara CA

H01L 21/3065
C23F 1/08

438719, 15634524, 257E21218

Embodiments of the invention provide a method and apparatus that enables plasma etching of high aspect ratio features. In one embodiment, a method for etching is provided that includes providing a substrate having a patterned mask disposed on a silicon layer in an etch reactor, providing a gas mixture of the reactor, maintaining a plasma formed from the gas mixture, wherein bias power and RF power provided the reactor are pulsed, and etching the silicon layer in the presence of the plasma.

20150096959, Apr 9, 2015

Oct 28, 2013

14/064890

- Santa Clara CA, US
Xiawan Yang - San Jose CA, US
Farid Abooameri - Pleasanton CA, US
Wen Teh Chang - Sunnyvale CA, US
Anisul H Khan - Santa Clara CA, US
Bradley Scott Hersch - Park City UT, US

APPLIED MATERIALS, INC. - Santa Clara CA

H01J 37/147
H01J 37/32

216 61

Etch rate distributions are captured at a succession of hardware tilt angles of the RF source power applicator relative to the workpiece and their non-uniformities computed, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset Δα in tilt angle α between the non-uniformity functions of the two plasma reactors is detected. The two plasma reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset Δα.

20150099314, Apr 9, 2015

Oct 28, 2013

14/064914

- Santa Clara CA, US
Xiawan Yang - San Jose CA, US
Farid Abooameri - Pleasanton CA, US
Wen Teh Chang - Sunnyvale CA, US
Anisul H. Khan - Santa Clara CA, US
Bradley Scott Hersch - Park City UT, US

APPLIED MATERIALS, INC. - Santa Clara CA

H01L 21/66
H01L 21/67
H01L 21/3065

438 9, 15634524

Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset Δα in tilt angle α between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset Δα.