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Eva M Selep

from Folsom, CA
Age ~65
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Also known as:
Eva Marie Selep, Jean Marie Selep, Eva M Trustees, Eva M Sleep
Phone and address:
111 Valley Falls Pl, Folsom, CA 95630
(916) 716-0617
Related to:
Jean Marie Selep
Connected to:
Elizabeth M Selep, 95Dennis J Selepak, 72Bettina L Seler, 34Brian D Seler, 58Hannah Selert, 34Catherine I Seles, 63Deborah G Seles, 73Justin L Seleska, 45Dana M Seleski, 36Elizabeth J Seleski, 89

Eva Selep Phones & Addresses

  • 111 Valley Falls Pl, Folsom, CA 95630 (916) 716-0617
  • Belmont, MA
  • Sacramento, CA
  • 111 Valley Falls Pl, Folsom, CA 95630

Work

Company: Western governors university Sep 2015 Position: Business faculty senior manager

Education

Degree: Master of Business Administration, Masters School / High School: California State University - Sacramento 1987 to 1994

Skills

Project Management • Management • Process Design • Higher Education Administration

Industries

Higher Education

Resumes

Resumes

Eva Selep Photo 1

Business Faculty Senior Manager

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Location:
111 Valley Falls Pl, Folsom, CA 95630
Industry:
Higher Education
Work:
Western Governors University
Business Faculty Senior Manager
Western Governors University Jun 2013 - Sep 2015
Business Faculty Manager
Western Governors University Dec 2010 - Jun 2013
Adjunct Faculty
Hewlett-Packard Jun 1995 - Jul 2003
Product Marketing
Hewlett-Packard Jun 1985 - Jun 1995
Process Engineer
Education:
California State University - Sacramento 1987 - 1994
Master of Business Administration, Masters Stanford University 1981 - 1982
Master of Science, Masters, Engineering University of Notre Dame 1977 - 1981
Bachelors, Bachelor of Science, Industrial Engineering
Skills:
Project Management
Management
Process Design
Higher Education Administration

Publications

Us Patents

High Mix Printed Circuit Assembly Technique

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US Patent:
51705540, Dec 15, 1992
Filed:
Sep 28, 1990
Appl. No.:
7/589748
Inventors:
Thomas C. Davis - Mountain View CA
Eva M. Selep - Folsom CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H05K 330
US Classification:
29832
Abstract:
A technique for efficient use of component placement apparatus used for assembling many different printed circuit boards, wherein all of the printed circuit boards are collectively comprised of more parts than can be handled by a single setup. A portion of the apparatus is dedicated to producing a first family of boards whose identity is determined by their high volume as well as by their parts overlap, while another portion is periodically changed in order to optionally produce different families of boards characterized by their lower volume and lower parts overlap. The changed setups required for the different families of boards are accomplished off-line while the first family of boards is in on-line production.
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Eva M Selep from Folsom, CA, age ~65 Get Report