Eun S Lee

D597248, Jul 28, 2009

Sep 25, 2008

29/325133

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Bank of America Corporation - Charlotte NC

2699

D26122

D601296, Sep 29, 2009

May 6, 2009

29/336608

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Bank of America Corporation - Charlotte NC

2699

D26122

D601297, Sep 29, 2009

May 6, 2009

29/336611

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Bank of America Corporation - Charlotte NC

2699

D26122

20220300797, Sep 22, 2022

Mar 16, 2021

17/203705

- Armonk NY, US
Eun Kyung Lee - Bedford Corners NY, US
Mingu Kang - Old Tappan NJ, US
Seonghoon Woo - NEW YORK NY, US

G06N 3/063
G06N 3/04
G06N 3/08
G11C 11/4063

An electronic circuit includes word lines; bit lines intersecting the word lines at a plurality of grid points; and resistive processing units located at the grid points. Baseline stochastic pulse input units are coupled to the word lines; differential stochastic pulse input units are coupled to the word lines; and bitline stochastic pulse input units are coupled to the bit lines. Control circuitry coupled to the pulse input units is configured to cause each of the baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from the base input data, and each of the bitline stochastic pulse input units to generate a bitline pulse train using bit line input data. Neural network weights can thus be stored in the resistive processing units.

20210208847, Jul 8, 2021

Jan 8, 2020

16/737440

- Armonk NY, US
Seyoung Kim - White Plains NY, US
Eun Kyung Lee - Bedford Corners NY, US

G06F 7/523
G06F 7/50
G06N 3/08

A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.

20200394186, Dec 17, 2020

Jun 11, 2019

16/437989

- Armonk NY, US
EUN KYUNG LEE - Yorktown Heights NY, US
ALESSANDRO MORARI - Yorktown Heights NY, US

G06F 16/2458
G06F 17/27
G06N 3/04
G06F 17/18

A method for context-aware data mining of a text document includes receiving a list of words parsed and preprocessed from an input query; computing a related distributed embedding representation for each word in the list of words using a word embedding model of the text document being queried; aggregating the related distributed embedding representations of all words in the list of words to represent the input query with a single embedding, by using one of an average of all the related distributed embedding representations or a maximum of all the related distributed embedding representations; retrieving a ranked list of document segments of N lines that are similar to the aggregated word embedding representation of the query, where N is a positive integer provided by the user; and returning the list of retrieved segments to a user.

20170277564, Sep 28, 2017

Mar 25, 2016

15/080689

- Armonk NY, US
Eun Kyung Lee - Elmsford NY, US
Yoonho Park - Chappaqua NY, US

G06F 9/48
G06F 9/50

A method, apparatus, and computer program product are provided for thermal- and spatial-aware task scheduling. The method may include monitoring a temperature for each core of a central processing unit having a plurality of cores; determining, from the monitoring, a set of hotspot cores from the plurality of cores determining temperature information and distance information for each hotspot core in the set of hotspot cores relative to each of the other cores on the central processing unit; calculating a placement metric for each core of the central processing unit based at least on the determined distance information and the determined temperature information; and scheduling a task by allocating the task to one or more cores of the central processing unit according to the placement metric.