Eui Jin Kim

8197636, Jun 12, 2012

Apr 21, 2008

12/106881

Ashish Shah - Santa Clara CA, US
Dale R. DuBois - Los Gatos CA, US
Ganesh Balasubramanian - Sunnyvale CA, US
Mark A. Fodor - Redwood City CA, US
Eui Kyoon Kim - Campbell CA, US
Chiu Chan - Foster City CA, US
Karthik Janakiraman - San Jose CA, US
Thomas Nowak - Cupertino CA, US
Joseph C. Werner - Santa Clara CA, US
Visweswaren Sivaramakrishnan - Cupertino CA, US
Mohamad Ayoub - San Jose CA, US
Amir Al-Bayati - San Jose CA, US
Jianhua Zhou - San Jose CA, US

Applied Materials, Inc. - Santa Clara CA

C23F 1/00
C23C 16/00
H01L 21/306

15634532, 15634531, 15634533, 15634534, 15634543, 118719, 118723 E

Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions.

20090017635, Jan 15, 2009

Jul 11, 2008

12/171708

Ashish Shah - Santa Clara CA, US
Ganesh Balasubramanian - Sunnyvale CA, US
Dale R. Du Bois - Los Gatos CA, US
Mark A. Fodor - Los Gatos CA, US
Eui Kyoon Kim - Campbell CA, US
Chiu Chan - Foster City CA, US
Karthik Janakiraman - San Jose CA, US
Thomas Nowak - Cupertino CA, US
Joseph C. Werner - Santa Clara CA, US
Visweswaren Sivaramakrishnan - Cupertino CA, US
Mohamad Ayoub - San Jose CA, US
Amir Al-Bayati - San Jose CA, US
Jianhua Zhou - San Jose CA, US

H01L 21/302
C23F 1/00

438729, 15634533, 257E21214

The present invention comprises an apparatus and method for etching at a substrate edge region. In one embodiment, the apparatus comprises a chamber having a process volume, a substrate support arranged inside the process volume and having a substrate support surface, a plasma generator coupled to the chamber and configured to supply an etching agent in a plasma phase to a peripheral region of the substrate support surface, and a gas delivery assembly coupled to a gas source for generating a radial gas flow over the substrate support surface from an approximately central region of the substrate support surface toward the peripheral region of the substrate support surface.

20090104541, Apr 23, 2009

Oct 23, 2007

11/877559

Eui Kyoon Kim - Campbell CA, US
Deenesh Padhi - Sunnyvale CA, US
Huixiong Dai - San Jose CA, US
Mehul Naik - San Jose CA, US
Martin Jay Seamons - San Jose CA, US
Bok Hoen Kim - San Jose CA, US

G03F 1/00

430 5

The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

20090197086, Aug 6, 2009

Feb 4, 2008

12/025615

Sudha Rathi - San Jose CA, US
Eui Kyoon Kim - Campbell CA, US
Bok Hoen Kim - San Jose CA, US
Martin Jay Seamons - San Jose CA, US
Francimar Campana Schmitt - Santa Clara CA, US

G03F 7/00
B05D 1/36
H05H 1/24
B32B 9/00

428408, 427402, 430324, 427569

A method and structure for the fabrication of semiconductor devices having feature sizes in the range of 90 nm and smaller is provided. In one embodiment of the invention, a method is provided for processing a substrate including depositing an anti-reflective coating layer on a surface of the substrate, depositing an adhesion promotion layer on the anti-reflective coating layer, and depositing a resist material on the adhesion promotion layer. In another embodiment of the invention, a semiconductor substrate structure is provided including a dielectric substrate, an amorphous carbon layer deposited on the dielectric layer, an anti-reflective coating layer deposited on the amorphous carbon layer, an adhesion promotion layer deposited on the anti-reflective coating layer, and a resist material deposited on the adhesion promotion layer.

20110111604, May 12, 2011

Jan 17, 2011

13/007963

Eui Kyoon Kim - Campbell CA, US
Deenesh Padhi - Sunnyvale CA, US
Huixiong Dai - San Jose CA, US
Mehul Naik - San Jose CA, US
Martin Jay Seamons - San Jose CA, US
Bok Hoen Kim - , US

H01L 21/31

438763, 257E2124

The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

20120211164, Aug 23, 2012

Apr 25, 2012

13/456080

Ashish Shah - Santa Clara CA, US
Dale R. DuBois - Los Gatos CA, US
Ganesh Balasubramanian - Sunnyvale CA, US
Mark A. Fodor - Los Gatos CA, US
Eui Kyoon Kim - Campbell CA, US
Chiu Chan - Foster City CA, US
Karthik Janakiraman - San Jose CA, US
Thomas Nowak - Cupertino CA, US
Joseph C. Werner - Santa Clara CA, US
Visweswaren Sivaramakrishnan - Cupertino CA, US
Mohamad Ayoub - Los Gatos CA, US
Amir Al-Bayati - San Jose CA, US
Jianhua Zhou - San Jose CA, US

Applied Materials, Inc. - Santa Clara CA

H01L 21/3065
C23C 16/458
C23C 16/50
H01L 21/306

15634531, 15634533, 118728, 118723 R

Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions.