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Eugenia M Atakov

from West Roxbury, MA
Age ~90
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Also known as:
Engenia Atakov, Tabov A Eugenia, Eugenia Atko, Takon A Eugenia, Eugenia Atakoy, Eugenia V
Phone and address:
1205 Centre St UNIT 412, Boston, MA 02132
Related to:
Rafael Castillo
Connected to:
Rachita Atal, 54Vijay R Atal, 41Munir A Atala, 45Elizabeth A Atalay, 58Yucel Atalay, 59Zeynep Atalay, 45Marie B Ataliede, 66Charlie Atalig, 36Christine M Atalig, 57Andrew S Atalla, 38

Eugenia Atakov Phones & Addresses

  • 1205 Centre St UNIT 412, West Roxbury, MA 02132
  • 130 Parker St, Acton, MA 01720 (978) 263-8774
  • Brookline, MA
  • Agawam, MA
  • Maynard, MA
  • 130 Parker St APT K4, Acton, MA 01720

Work

Company: Ibm/rational 2000 to 2007 Position: Software quality engineer

Education

Degree: BS, MS School / High School: Moscow Institute of Energy Specialities: Electrical Engineering

Industries

Computer Software

Resumes

Resumes

Eugenia Atakov Photo 1

Moscow Institute Of Energy

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Location:
Boston, MA
Industry:
Computer Software
Work:
IBM/Rational 2000 - 2007
Software Quality Engineer
Epsilon Software 1999 - 2000
Software QA analyst
Intel Corp. 1998 - 1999
Senior process engineer
Digital Equipment Corporation 1988 - 1998
principal engineer
Education:
Moscow Institute of Energy
BS, MS, Electrical Engineering

Publications

Us Patents

Method Of Forming Electrical Interconnects Having Electromigration-Inhibiting Plugs

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US Patent:
6678951, Jan 20, 2004
Filed:
Dec 12, 2000
Appl. No.:
09/735566
Inventors:
Eugenia Atakov - Acton MA
Adam Shepela - Bolton MA
Lawrence Bair - Littleton MA
John Clement - Westboro MA
Bruce Gieseke - Ashland MA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H05K 302
US Classification:
29847, 29852, 29DIG 16, 174250, 174255
Abstract:
A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Alternatively, windows may be formed in a dielectric layer and the conductive segments formed from electrically conductive material deposited in trenches in the dielectric between neighboring windows, the plugs, conductive segments and dielectric surface being coplanar. Embodiments of the method may be employed in manufacture of integrated circuit conductors.

Method Of Forming Electrical Interconnects Having Electromigration-Inhibiting Plugs

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US Patent:
6904675, Jun 14, 2005
Filed:
Oct 1, 2003
Appl. No.:
10/676443
Inventors:
Eugenia Atakov - Acton MA, US
Adam Shepela - Bolton MA, US
Lawrence Bair - Littleton MA, US
John Clement - Westboro MA, US
Bruce Gieseke - Ashland MA, US
Assignee:
Hewlett-Packard Development, L.P. - Houston TX
International Classification:
H01K003/10
US Classification:
29852, 29825, 29846, 438623, 438627, 438633, 438643, 438648, 438656, 438680, 438681, 438780, 438781
Abstract:
A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide, electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Alternatively, windows may be formed in a dielectric layer and the conductive segments formed from electrically conductive material deposited in trenches in the dielectric between neighboring windows, the plugs, conductive segments and dielectric surface being coplanar. Embodiments of the method may be employed in manufacture of integrated circuit conductors.

Method Of Forming Electrical Interconnects Having Electromigration-Inhibiting Segments To A Critical Length

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US Patent:
7062850, Jun 20, 2006
Filed:
Oct 8, 2003
Appl. No.:
10/681843
Inventors:
Eugenia Atakov - Acton MA, US
Adam Shepela - Bolton MA, US
Lawrence Bair - Littleton MA, US
John Clement - Westboro MA, US
Bruce Gieseke - Ashland MA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H05K 3/10
H01L 21/441
C23C 20/02
US Classification:
29852, 29846, 29831, 427 972, 427 977, 438675
Abstract:
A method of forming an electrical conductor, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigraation-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Embodiments of the method may be employed in manufacture of integrated circuit conductor.

Electrical Interconnect Structure Having Electromigration-Inhibiting Segments

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US Patent:
62459961, Jun 12, 2001
Filed:
May 20, 1999
Appl. No.:
9/316916
Inventors:
Eugenia Atakov - Acton MA
Adam Shepela - Bolton MA
Lawrence Bair - Littleton MA
John Clement - Westboro MA
Bruce Gieseke - Ashland MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
H01B 100
H05K 100
US Classification:
174 681
Abstract:
An integrated circuit is formed having electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. Windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs. The plugs are formed at a distance less than, or equal to, the predetermined critical length, L. sub.

Integrated Circuit Metal Film Interconnect Having Enhanced Resistance To Electromigration

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US Patent:
53828313, Jan 17, 1995
Filed:
Dec 14, 1992
Appl. No.:
7/990222
Inventors:
Eugenia M. Atakov - Acton MA
John J. Clement - Westboro MA
Brian C. Lee - Northboro MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H01L 2348
H01L 2940
US Classification:
257767
Abstract:
For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line. The predetermined length should be about ten to twenty times the mean length of polycrystalline segments in a line of the minimum linewidth. For a 1. 25. mu. m minimum linewidth and a 7,600. ANG.
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Eugenia M Atakov from West Roxbury, MA, age ~90 Get Report