Inventors:
Eugene L. Shrock - Castle Rock CO
William K. Petty - Colorado Springs CO
Assignee:
NCR Corporation - Dayton OH
International Classification:
H03K 3286
H03K 3289
Abstract:
A data synchronizer that operates at two to four times greater clock and data rates than previous data synchronizers. By using a positive feedback, self latching gate as the first memory element, rather than a cross-coupled device such as a flip-flop, such rates are attained without inducing metastable oscillation. The positive feedback, self latching gate is far less prone to metastable oscillation since it does not have two cross-coupled devices fighting each other to resolve the proper response to an input. Instead, the self latching gate latches up if a data HIGH is present during a clock HIGH, and remains LOW otherwise. External circuitry resets the self latching gate to the LOW state before the start of each clock HIGH cycle to remove any previous latched state. The self latching gate output is then synchronously sampled by a type D flip-flop to provide a completely synchronized data output.
