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Esin Kutlu Demirlioglu

from Cupertino, CA
Age ~69
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Also known as:
Esin K Demirlioglu, Ek Demirlioglu, Demirlioglu Esin, Demirlioglu Ek
Phone and address:
10229 Glencoe Dr, Cupertino, CA 95014
(408) 366-1993
Related to:
Baris DemirliogluDuygu Demirlioglu, 83Duygu Demirlioglu, 82Ozan Demirlioglu, 39
Connected to:
Ramazan Demirli, 54Alma Demirovic, 39Bekim Demirovic, 35Ilvana Demirovic, 40Jasmina Demirovic, 58Muris Demirovic, 46Raisa Demirovic, 37Skender S Demirovic, 70Errol A Demirsu, 67Sefa Demirtas, 40

Esin Demirlioglu Phones & Addresses

  • 10229 Glencoe Dr, Cupertino, CA 95014 (408) 366-1993
  • Fremont, CA
  • Palo Alto, CA
  • Cary, NC

Skills

Manufacturing

Languages

Russian

Interests

Nascar • Home Improvement • Donor • Shooting • Gourmet Cooking • Sports • Reading • Golf • Home Decoration • Photograph • Cooking • Electronics • Outdoors • Crafts • Music • Movies • Collecting • Kids • Travel • Career • Investing • Traveling • International Traavel

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Esin Demirlioglu Photo 1

Esin Demirlioglu

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Location:
10229 Glencoe Dr, Cupertino, CA 95014
Industry:
Electrical/Electronic Manufacturing
Skills:
Manufacturing
Interests:
Nascar
Home Improvement
Donor
Shooting
Gourmet Cooking
Sports
Reading
Golf
Home Decoration
Photograph
Cooking
Electronics
Outdoors
Crafts
Music
Movies
Collecting
Kids
Travel
Career
Investing
Traveling
International Traavel
Languages:
Russian

Publications

Us Patents

Floating Gate Structure With High Electrostatic Discharge Performance

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US Patent:
20070236843, Oct 11, 2007
Filed:
Jan 18, 2007
Appl. No.:
11/655493
Inventors:
Esin Demirlioglu - Cupertino CA, US
International Classification:
H02H 9/00
US Classification:
361056000
Abstract:
Systems and methods for floating gate structures with high electrostatic discharge performance. In one embodiment, a semiconductor structure includes a floating field gate device. The floating field gate device includes an embedded diode characterized as having less temperature dependence than a Zener diode. The breakdown voltage of the embedded diode is greater than an operating voltage of an associated integrated circuit and a snapback trigger voltage of the embedded diode is lower than a breakdown voltage of the semiconductor structure.

High Voltage Mos Device Having An Extended Drain Region With Different Dopant Species

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US Patent:
60911115, Jul 18, 2000
Filed:
Sep 19, 1996
Appl. No.:
8/715711
Inventors:
Esin Kutlu Demirlioglu - Cary NC
Monir H. El-Diwany - Saratoga CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2976
H01L 2994
H01L 31062
US Classification:
257344
Abstract:
A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3. 5. times. 10. sup. 17 cm. sup. -3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region.

Process For Incorporating Silicon Oxynitride Darc Layer Into Formation Of Silicide Polysilicon Contact

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US Patent:
60637048, May 16, 2000
Filed:
Aug 2, 1999
Appl. No.:
9/366033
Inventors:
Esin K. Demirlioglu - Cupertino CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2144
H01L 214763
US Classification:
438664
Abstract:
A process flow for forming a silicided polysilicon feature avoids removal of the SiON dielectric anti-reflective coating (DARC) used to pattern the polysilicon. Instead, following polysilicon formation and etching aided by the DARC, the DARC is modified to enrich its silicon content. This modification may take the form of densification by annealing in conjunction with formation of a seal oxide, densification by annealing in an inert ambient prior to exposure to oxidizing conditions, or direct ion implantation of semiconductor material into the DARC. As a result of this modification, the DARC becomes sufficiently enriched in semiconductor material to permit formation of silicide. Thermal densification of DARC during formation of a seal oxide is sufficient to permit formation of silicide upon exposure to a silicide-forming metal. In this embodiment however, implantation of semiconductor material prior to silicide formation is generally necessary to permit silicidation of a thin oxide layer created between DARC and polysilicon as a by-product of the prior thermal seal oxidation step.

Trench Refill With Selective Polycrystalline Materials

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US Patent:
59947187, Nov 30, 1999
Filed:
Aug 13, 1997
Appl. No.:
8/910811
Inventors:
Esin Kutlu Demirlioglu - Cupertino CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2904
H01L 2900
US Classification:
257 65
Abstract:
A trench refill for a semiconductor device is undertaken by depositing polycrystalline Ge or Ge. sub. x Si. sub. 1-x alloy at temperatures as low as 500. degree. C. The structure is then oxidized at for example 700. degree. C. to obtain a cap oxide on the trench refill. This method causes avoidance of (1) void formation, (2) facet formation, and (3) necessity of a second insulator deposition and planarization, meanwhile achieving all these advantages at a low thermal budget.

Co-Implantation Of Arsenic And Phosphorus In Extended Drain Region For Improved Performance Of High Voltage Nmos Device

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US Patent:
58937420, Apr 13, 1999
Filed:
Sep 19, 1996
Appl. No.:
8/724293
Inventors:
Esin Kutlu Demirlioglu - Cary NC
Monir H. El-Diwany - Saratoga CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21336
US Classification:
438307
Abstract:
A high voltage NMOS device includes an extended drain region formed by implantation of arsenic and phosphorus and a drivein of both the species. The dosage of arsenic is substantially higher than the dosage of phosphorus, so that upon drivein, the slower diffusing arsenic is highly concentrated near the surface of the extended drain region, while the more rapidly diffusing phosphorus provides a gradual gradient of concentration of dopant into the extended drain region.

Defect Free Cmos Process

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US Patent:
55717446, Nov 5, 1996
Filed:
Aug 27, 1993
Appl. No.:
8/113787
Inventors:
Esin K. Demirlioglu - Cupertino CA
Sheldon Aronowitz - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
H01L 2170
H01L 2700
H01L 21225
US Classification:
437 57
Abstract:
A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.
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Esin Kutlu Demirlioglu from Cupertino, CA, age ~69 Get Report