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Erik J Roggeman

from Indianapolis, IN
Age ~50
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Also known as:
Erik Leah Roggeman, Erik M Roggeman, Erik L Roggeman, Leah M Roggeman, Eric A Roggeman, Erik J Roggemann, Erik N, H Roggeman
Phone and address:
6917 Bluffgrove Ln, Indianapolis, IN 46278
(317) 299-0089
Related to:
Peyton P Huene, 27Susan R Roggeman, 72Michael D Stephenson, 39Philip RoggemanNicole Roggeman, 73Ann M Roggeman, 75Narcizo G RomeroDonald W Stephenson, 78Andrew A Roggeman, 73Edward R Roggeman, 64L M RoggemanNicole S Roggeman, 49Leah L Stephenson, 49
Connected to:
Alex D Roggeman, 28Alfred C Roggeman, 86Carin A Roggeman, 43Cassie D Roggemann, 38Darren W Roggeman, 59Peggy Roggemann, 122Sarah Roggemann, 34Abby R Roggenbaum, 27Amy S Roggenbuck, 50Edgar G Roggen, 90

Erik Roggeman Phones & Addresses

  • 6917 Bluffgrove Ln, Indianapolis, IN 46278 (317) 299-0089
  • 27 Bayberry Cir, Fishkill, NY 12524 (845) 896-1411
  • Wappingers Falls, NY
  • South Bend, IN
  • Belmont, CA

Work

Company: Eli lilly and company Apr 2013 Position: Director - quality assurance

Education

Degree: Master of Science, Masters School / High School: University of Notre Dame 1996 to 1998 Specialities: Chemical Engineering

Skills

Validation • Gmp • Change Control • Pharmaceutical Industry • Capa • Fda • Computer System Validation • Quality Assurance • Technology Transfer • 21 Cfr Part 11 • Gxp • V&V • Six Sigma • Quality Auditing • Quality System • Analytical Chemistry • Chemistry • Root Cause Analysis • Chromatography • Quality Management • Process Improvement • Sop • Hplc • Quality Control • Biotechnology • Cross Functional Team Leadership • Drug Development • Gamp • Aseptic Processing • Spc • R&D • Clinical Trials • Biopharmaceuticals • Project Management • Process Optimization • Process Simulation • Lifesciences • Manufacturing • Regulatory Submissions • Operational Excellence • Design of Experiments • Clinical Development • Fmea • Lean Manufacturing • Process Engineering • Process Control • Iso 13485 • Cleaning Validation • Lims • Gas Chromatography

Industries

Pharmaceuticals

Resumes

Resumes

Erik Roggeman Photo 1

Director - Quality Assurance

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Location:
Elmhurst, IL
Industry:
Pharmaceuticals
Work:
Eli Lilly and Company
Director - Quality Assurance
Eli Lilly and Company Dec 2011 - Mar 2013
Manager - Quality Assurance
Eli Lilly and Company Dec 2008 - Nov 2011
Associate Quality Consultant
Eli Lilly and Company Apr 2004 - Nov 2008
Associate Technical Consultant
Ibm Sep 1, 1998 - Dec 31, 2004
Senior Process Engineer
Education:
University of Notre Dame 1996 - 1998
Master of Science, Masters, Chemical Engineering Rose - Hulman Institute of Technology 1992 - 1996
Bachelors, Bachelor of Science, Chemical Engineering York Community High School
Skills:
Validation
Gmp
Change Control
Pharmaceutical Industry
Capa
Fda
Computer System Validation
Quality Assurance
Technology Transfer
21 Cfr Part 11
Gxp
V&V
Six Sigma
Quality Auditing
Quality System
Analytical Chemistry
Chemistry
Root Cause Analysis
Chromatography
Quality Management
Process Improvement
Sop
Hplc
Quality Control
Biotechnology
Cross Functional Team Leadership
Drug Development
Gamp
Aseptic Processing
Spc
R&D
Clinical Trials
Biopharmaceuticals
Project Management
Process Optimization
Process Simulation
Lifesciences
Manufacturing
Regulatory Submissions
Operational Excellence
Design of Experiments
Clinical Development
Fmea
Lean Manufacturing
Process Engineering
Process Control
Iso 13485
Cleaning Validation
Lims
Gas Chromatography

Publications

Us Patents

Barrier For Interconnect And Method

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US Patent:
6992389, Jan 31, 2006
Filed:
Apr 28, 2004
Appl. No.:
10/709321
Inventors:
Panayotis C. Andricacos - Croton-on-Hudson NY, US
Tien-Jen J. Cheng - Bedford NY, US
Emanuel I. Cooper - Scarsdale NY, US
David E. Eichstadt - Park Ridge IL, US
Jonathan H. Griffith - Lagrangeville NY, US
Randolph F. Knarr - Goldens Bridge NY, US
Roger A. Quon - Rhinebeck NY, US
Erik J. Roggeman - Fishkill NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/48
H01L 23/52
H01L 21/60
H01L 23/485
US Classification:
257746, 257751, 257753, 257766, 257767, 257762, 257E23021, 257E21508, 257E21586
Abstract:
A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Sacrificial Seed Layer Process For Forming C4 Solder Bumps

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US Patent:
20030155408, Aug 21, 2003
Filed:
Feb 19, 2002
Appl. No.:
10/078948
Inventors:
Lisa Fanti - Hopewell Junction NY, US
Randolph Knarr - Goldens Bridge NY, US
Erik Roggeman - Fishkill NY, US
Kamalesh Srivastava - Wappingers Falls NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
B23K031/02
B23K035/12
US Classification:
228/215000, 228/246000, 228/180220
Abstract:
Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next. Form C4 solder bumps on the plating sites on the base/barrier layer within the C4 solder bump openings, with the C4 solder bumps being in contact with the conductive metal layer on the periphery of the through holes. Remove the mask. Etch away the remainder of the conductive metal layer, and etch away the base aside from the C4 solder bumps forming BLM pads. Then reflow the C4 solder bumps to form C4 solder balls.
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Erik J Roggeman from Indianapolis, IN, age ~50 Get Report