Erik P Machnicki

7249202, Jul 24, 2007

Jul 26, 2004

10/899196

Moshe B. Simon - San Ramon CA, US
Erik P. Machnicki - Sunnyvale CA, US
Mark Longley - Livermore CA, US

Cradle Technologies, Inc. - Sunnyvale CA

G06F 13/28
G06F 3/00

710 22, 710 30, 710 36, 710 52, 709212, 709250

A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.

7716269, May 11, 2010

Jun 16, 2005

11/153979

Moshe B. Simon - San Ramon CA, US
Erik P. Machnicki - Sunnyvale CA, US
David A. Harrison - Cupertino CA, US
Rakesh K. Singh - Pune, IN

Cradle Technologies - Mountain View CA

G06F 7/38

708523

A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

8120377, Feb 21, 2012

Jun 26, 2009

12/492427

Jianlin Yu - Cupertino CA, US
Michael Frank - Sunnyvale CA, US
Erik P. Machnicki - San Jose CA, US
Jerrold V. Hauck - Windermere FL, US
Jean-Didier Allegrucci - Sunnyvale CA, US
Santiago Fernandez-Gomez - Sunnyvale CA, US

Apple Inc. - Cupertino CA

G01R 31/26

32476201, 3247503

Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.

8151008, Apr 3, 2012

Jul 2, 2008

12/167096

Moshe B. Simon - San Ramon CA, US
Erik P. Machnicki - San Jose CA, US
David A. Harrison - Cupertino CA, US

Cradle IP, LLC - Mountain View CA

G06F 13/28
G06F 13/30

710 6, 710 5, 710 22, 710 40, 710 41

A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.

8190942, May 29, 2012

Jul 2, 2008

12/167111

Moshe B. Simon - San Ramon CA, US
Erik P. Machnicki - San Jose CA, US

Cradle IP, LLC - Mountain View CA

G06F 1/12

713400

A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code over a global timebase bus. A global timebase generator includes a binary counter and a binary-to-Gray-code converter. Each receiver module registers the global timebase count value with its own local clock and includes a Gray-code-to-binary converter. The converted value, in binary form, may be used as least significant bits of a globally synchronized local timebase. Most significant bits may be generated by a local binary counter incremented at each 1-to-0 transition of the most significant bit of the global timebase count value.

8310291, Nov 13, 2012

Nov 17, 2010

12/948192

Erik P. Machnicki - San Jose CA, US
James D. Ramsay - San Jose CA, US
Sanjay Mansingh - Santa Clara CA, US

Apple Inc. - Cupertino CA

H03L 7/06

327158, 327156, 327161

A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.

8417983, Apr 9, 2013

Dec 6, 2010

12/960708

Erik P. Machnicki - San Jose CA, US
Timothy J. Millet - Mountain View CA, US
Stephan Vincent Schell - San Mateo CA, US

Apple Inc. - Cupertino CA

G06F 1/00
G06F 1/04
G06F 3/033
H03K 3/03
H03K 19/00
H03K 9/00
H03B 25/00
H04L 27/00
H04H 20/71
H04B 1/38

713500, 713300, 713600, 331 46, 331 60, 326 93, 375295, 375316, 455 301, 455 73, 455130

Adjusting a clock source of a device clock to reduce wireless communication (e. g. , radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e. g. , coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.

8468373, Jun 18, 2013

Jan 14, 2011

13/006967

Erik P. Machnicki - San Jose CA, US
Timothy J. Millet - Mountain View CA, US
Josh P. de Cesare - Campbell CA, US

Apple Inc. - Cupertino CA

G06F 1/00

713300, 713322

Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.