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Erich W Lowe

from Austin, TX
Age ~60
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Also known as:
Erich Werner Lowe, Eric W Lowe, Eric K Lowe, Erich W Loue, Erick Lowe
Phone and address:
7813 Harvestman Cv, Austin, TX 78731
(512) 346-2344
Related to:
Terrence S Lowe, 50Paula D Lowe, 60Kevin J Eisaman, 63Karen E Hoffman, 65Kurt W Lowe, 63Roland A Lowe, 66Karen E Lowe, 65Linda K Hendrickson, 63
Connected to:
Aariel Lowe, 34Ace Lowe, 40Achika LoweAda M Lowe, 46Adeja S Lowe, 36Alene Lowe, 66Alta F Lowe, 69Altobis R Lowe, 47Amber Lowe, 38Amiee R Lowe, 43

Erich Lowe Phones & Addresses

  • 7813 Harvestman Cv, Austin, TX 78731 (512) 346-2344
  • Granite Shoals, TX
  • Ronkonkoma, NY
  • Huntington, NY
  • North Royalton, OH
  • San Antonio, TX
  • 7813 Harvestman Cv, Austin, TX 78731 (512) 970-1108

Work

Company: Freescale semiconductor Jul 2008 to Jul 2012 Position: Design engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Cornell University 1983 to 1987

Skills

Soc • Asic • Rtl Design • Functional Verification • Ic • Debugging • Semiconductors • Verilog • Firmware • Device Drivers • Digital Signal Processors • Arm

Emails

e***[email protected]

Industries

Semiconductors

Resumes

Resumes

Erich Lowe Photo 1

Senior Design Engineer

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Location:
7000 north Mo Pac Expy, Austin, TX 73301
Industry:
Semiconductors
Work:
Freescale Semiconductor Jul 2008 - Jul 2012
Design Engineer
Calxeda, Inc. Jul 2008 - Jul 2012
Senior Design Engineer
Sigmatel Jul 2003 - Jul 2008
Engineer
Equator Technology 1998 - 2003
Design Engineer
Infotronics 1995 - 1996
Design Engineer
Education:
Cornell University 1983 - 1987
Bachelors, Bachelor of Science
Skills:
Soc
Asic
Rtl Design
Functional Verification
Ic
Debugging
Semiconductors
Verilog
Firmware
Device Drivers
Digital Signal Processors
Arm

Publications

Us Patents

Radio Receiver, System On A Chip Integrated Circuit And Methods For Use Therewith

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US Patent:
7391347, Jun 24, 2008
Filed:
Nov 22, 2005
Appl. No.:
11/287572
Inventors:
Michael R. May - Austin TX, US
Erich Lowe - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H03M 1/48
US Classification:
341117, 341110
Abstract:
A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

Digital Clock Controller, Radio Receiver, And Methods For Use Therewith

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US Patent:
7620131, Nov 17, 2009
Filed:
Nov 22, 2005
Appl. No.:
11/287549
Inventors:
Michael R. May - Austin TX, US
Erich Lowe - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H04B 1/10
US Classification:
375349, 375316, 375354, 327144, 341117
Abstract:
A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

Radio Receiver, System On A Chip Integrated Circuit And Methods For Use Therewith

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US Patent:
7656968, Feb 2, 2010
Filed:
Nov 22, 2005
Appl. No.:
11/287571
Inventors:
Erich Lowe - Austin TX, US
Michael R. May - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H03K 9/00
H04L 27/00
US Classification:
375316, 375327, 375354, 375373, 375376
Abstract:
A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

Radio Receiver, System On A Chip Integrated Circuit And Methods For Use Therewith

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US Patent:
7672403, Mar 2, 2010
Filed:
Nov 22, 2005
Appl. No.:
11/287570
Inventors:
Michael R. May - Austin TX, US
Erich Lowe - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H03K 9/00
H04L 27/00
US Classification:
375316, 375147, 375326, 375354
Abstract:
A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

Radio Receiver, System On A Chip Integrated Circuit And Methods For Use Therewith

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US Patent:
7684515, Mar 23, 2010
Filed:
Nov 22, 2005
Appl. No.:
11/287551
Inventors:
Michael R. May - Austin TX, US
Erich Lowe - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H03K 9/00
H04L 27/00
US Classification:
375316, 375136, 375147, 375324, 375326, 375340
Abstract:
A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period.

Integrated Circuit Having Radio Receiver And Methods For Use Therewith

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US Patent:
8130871, Mar 6, 2012
Filed:
Jan 9, 2006
Appl. No.:
11/328830
Inventors:
Michael R. May - Austin TX, US
Erich Lowe - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
H04L 27/00
H03M 1/48
H03M 3/00
H03M 1/12
US Classification:
375316, 375322, 375326, 341117, 341143, 341155
Abstract:
An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

Clock Generator, System On A Chip Integrated Circuit And Methods For Use Therewith

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US Patent:
20070115039, May 24, 2007
Filed:
Nov 22, 2005
Appl. No.:
11/287550
Inventors:
Erich Lowe - Austin TX, US
Michael May - Austin TX, US
International Classification:
G06F 1/04
US Classification:
327291000
Abstract:
A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.
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Erich W Lowe from Austin, TX, age ~60 Get Report