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Eric R Wehage

from Tenino, WA
Age ~52
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Also known as:
Eric Rodger Wehage, Eric E Wehage, Eric W Wehage, Emage W Eric
Phone and address:
15140 Palmer Ln, Tenino, WA 98589
(360) 446-3657
Related to:
Kenneth Leon Madison, 69Anthony E MadisonGwendolyn L Wehage, 72Joseph Wehage, 50Rodger J Wehage, 75Tracy R Wehage, 49Tracey WehageShannalee M Wehage, 48Stephanie L Bittick, 41Kinaeth Q Madison, 47
Connected to:
Ernst L Wehausen, 80Kathleen A Wehba, 88Darine Wehbe, 46Fadwa Wehbe, 66Jamil E Wehbe, 37Michael Wehbe, 68Sahar S Wehbe, 51Tarek S Wehbe, 44Tracey A Wehbey, 59Amal K Wehbi, 58

Eric Wehage Phones & Addresses

  • 15140 Palmer Ln, Tenino, WA 98589 (360) 446-3657
  • Sequim, WA
  • Yamhill, OR
  • Gaston, OR
  • 4533 Masters Loop, Aloha, OR 97007 (503) 642-3426
  • Beaverton, OR
  • Rainier, WA
  • New York, NY
  • Florence, SC
  • 15140 Palmer Ln SE, Tenino, WA 98589

Work

Company: Futurewei technologies Sep 2016 Position: Principal engineer, pcie

Education

Degree: Bachelors School / High School: Oregon State University 1990 to 1994 Specialities: Electronics Engineering, Electronics

Skills

Computer Architecture • Processors • Debugging • Hardware Architecture • Pcie • Application Specific Integrated Circuits • Verilog • Rtl Design • System on A Chip • Soc • Asic • System Architecture • Embedded Systems • Microprocessors • Semiconductors • Intel • Ic • Perl • Firmware • Vlsi • C • Virtualization • Microcontrollers • Fpga • Integrated Circuits • Vhdl • Field Programmable Gate Arrays • Very Large Scale Integration • Storage Solutions • C Programming

Languages

English

Industries

Semiconductors

Resumes

Resumes

Eric Wehage Photo 1

Principal Engineer, Pcie

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Location:
15140 Palmer Ln southeast, Tenino, WA 98589
Industry:
Semiconductors
Work:
Futurewei Technologies
Principal Engineer, Pcie
Intel Corporation 2015 - 2016
Stormlake Fabric Architect
Intel Corporation 2008 - 2015
Cpu I and O Architect
Intel Corporation 2004 - 2008
Micro-Architect For Manageability Engine Integration Into Pch
Intel Corporation 2002 - 2004
Esb2 Chipset Micro-Architect and Designer
Education:
Oregon State University 1990 - 1994
Bachelors, Electronics Engineering, Electronics
Skills:
Computer Architecture
Processors
Debugging
Hardware Architecture
Pcie
Application Specific Integrated Circuits
Verilog
Rtl Design
System on A Chip
Soc
Asic
System Architecture
Embedded Systems
Microprocessors
Semiconductors
Intel
Ic
Perl
Firmware
Vlsi
C
Virtualization
Microcontrollers
Fpga
Integrated Circuits
Vhdl
Field Programmable Gate Arrays
Very Large Scale Integration
Storage Solutions
C Programming
Languages:
English

Publications

Us Patents

Method And Apparatus For A Configuration Ring

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US Patent:
6820158, Nov 16, 2004
Filed:
Aug 30, 1999
Appl. No.:
09/385978
Inventors:
David M. Lee - Portland OR
Kyle T. McCanta - Beaverton OR
Eric R. Wehage - Tenino WA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1314
US Classification:
710305, 710107, 370258, 709251
Abstract:
A method and apparatus for a configuration ring is described. The method and apparatus include a configuration ring including a master, a first target, and a second target, the master coupled to the first target through a ring, the first target coupled to the second target through the ring, and the second target coupled to the master through the ring. The method and apparatus also include a method of using the configuration ring including originating a packet, passing the packet, decoding the packet, and utilizing the packet. The method and apparatus also includes a system including a processor, and processor bus coupled to the processor, a data chip coupled to the processor bus, a address chip coupled to the processor bus and the data chip, the address chip having a configuration ring, the configuration ring having a master, a first target and a second target, the master coupled through a ring to the first target, the first target coupled through the ring to the second target, the second target coupled through the ring to the master.

Low Cost Built-In Self Test State Machine For General Purpose Ram Testing

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US Patent:
6941495, Sep 6, 2005
Filed:
Feb 15, 2002
Appl. No.:
10/078065
Inventors:
Eric R. Wehage - Tenino WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C029/00
US Classification:
714718, 714 30, 365201, 326 46
Abstract:
A system and method for creating a built-in self-testing (BIST) state machine to test random access memories (RAMs) are disclosed. The BIST state machine can be simplified to a simple four-state state machine while accommodating a large group of test suites by programming each state to have the capability of performing one of four necessary operations. These operations include a write operation, a read operation, a read/write operation and a null operation. Further bits and signals can be added to the state machine to enable an even larger array of test suites to be performed.

Leakage Testing For Differential Signal Transceiver

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US Patent:
7019550, Mar 28, 2006
Filed:
Jun 29, 2004
Appl. No.:
10/879788
Inventors:
Eric R. Wehage - Tenino WA, US
Anne Meixner - Portland OR, US
Kersi H. Vakil - Olympia WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/00
US Classification:
326 16, 326 9, 326 15
Abstract:
A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.

General Input/Output Architecture, Protocol And Related Methods To Manage Data Integrity

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US Patent:
7152128, Dec 19, 2006
Filed:
Aug 23, 2002
Appl. No.:
10/227600
Inventors:
Eric R. Wehage - Tenino WA, US
Jasmin Ajanovic - Portland OR, US
David Harriman - Portland OR, US
David M. Lee - Portland OR, US
Blaise Fanning - El Dorado Hills CA, US
Buck Gremel - Olympia WA, US
Ken Creta - Cig Harbor WA, US
Wayne Moore - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/14
US Classification:
710305
Abstract:
An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.

General Input/Output Architecture, Protocol And Related Methods To Manage Data Integrity

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US Patent:
7353313, Apr 1, 2008
Filed:
Oct 23, 2006
Appl. No.:
11/585648
Inventors:
Eric R. Wehage - Tenino WA, US
Jasmin Ajanovic - Portland OR, US
David Harriman - Portland OR, US
David M. Lee - Portland OR, US
Blaise Fanning - El Dorado Hills CA, US
Buck Gremel - Olympia WA, US
Ken Creta - Gig Harbor WA, US
Wayne Moore - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/14
US Classification:
710305
Abstract:
An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e. g. , implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.

Methodology For Detecting Lost Packets

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US Patent:
20030066016, Apr 3, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/968275
Inventors:
Eric Wehage - Tenino WA, US
International Classification:
H03M013/00
US Classification:
714/781000
Abstract:
A system and method are described for detecting packet loss using an error checking signature, such as a cyclical redundancy check (CRC), while transmitting packets between a sender and a receiver. A counter is present on both the sender and the receiver, the two counters initially synchronized with each other. The CRC is generated using a sequence number provided by the counter at the sender. As the packets are sent, the sender counter is incremented. The receiver uses a sequence number from the receiver counter to decode the CRC. If all the packets are received, the sequence number to decode should match the sequence number to encode. Therefore, if the CRC does not decode properly, a packet has been lost or corrupted. A message to resend the packets is sent to the sender. The receiver counter is not incremented until the proper packet is received and decoded.

Built-In Self Test Parallel Jtag Serial Chain Architecture For Reduced Test Vector Size

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US Patent:
20030172333, Sep 11, 2003
Filed:
Mar 8, 2002
Appl. No.:
10/095359
Inventors:
Eric Wehage - Tenino WA, US
International Classification:
G01R031/28
US Classification:
714/726000, 714/733000
Abstract:
A system and method for programming built-in self-testing (BIST) state machines to test integrated circuit components are disclosed. The standard Joint Test Action Group method for programming BIST state machines is modified to increase speed and efficiency. The registers containing the instructions for BIST testing are connected in parallel, as opposed to the standard serial connections, allowing the registers to be fed instructions simultaneously. This cuts down the required time to feed test instructions to the BIST state machines. The addition of multiple shadow registers to each register further cuts down the required time to feed test instructions to the BIST state machines.

Methods And Apparatus To Protect Segments Of Memory

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US Patent:
20120023364, Jan 26, 2012
Filed:
Jul 26, 2010
Appl. No.:
12/843617
Inventors:
Robert C. Swanson - Olympia WA, US
Eric R. Wehage - Tenino WA, US
Vincent J. Zimmer - Federal Way WA, US
Mallik Bulusu - Olympia WA, US
International Classification:
G06F 11/14
US Classification:
714 612, 714E11113
Abstract:
Methods and apparatus to protect segments of memory are disclosed herein. An example method includes intercepting an interrupt request indicating an error; determining whether a first segment of memory is corrupt, the first segment of memory being designated as a protected region of memory; when the protected region of memory is corrupt, repairing the corrupted region of memory using a parity block of code; and in response to validating the protected region of memory, generating an interrupt enabling a utilization of code stored in the protected region of memory to handle the error associated with the interrupt request.
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Eric R Wehage from Tenino, WA, age ~52 Get Report