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Eric G Ryan

from Marina del Rey, CA
Age ~47
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Also known as:
Ryan Eric
Phone and address:
13900 Panay Way APT R203, Venice, CA 90292
Related to:
Judy Ann Smullen, 60Betty J Ryan, 98Marguerita Ryan, 62M J Ryan, 40Matthew C Ryan, 40M RyanMarguerita L Ryan, 71Jamesf AbbottJames Frederick AbbottMark Ryan, 73
Connected to:
Abraham A Ryan, 74Adeline Ryan, 109Alannah S Ryan, 48Alen K Ryan, 52Alexa Ryan, 34Alexandria Ryan, 57Allyson K Ryan, 39Alma G Ryan, 77Ambrose J Ryan, 96Amy R Ryan, 45

Eric Ryan Phones & Addresses

  • 13900 Panay Way APT R203, Marina Dl Rey, CA 90292
  • Marina del Rey, CA
  • Mountain View, CA
  • Montrose, CA
  • North Hollywood, CA
  • 913 N Mountain View Pl, Fullerton, CA 92831 (714) 936-4051
  • Berkeley, CA
  • Los Angeles, CA
  • Glendale, CA

Professional Records

License Records

Eric Thomas Ryan

License #:
9604 - Active
Issued Date:
Oct 31, 1985
Renew Date:
Dec 1, 2015
Expiration Date:
Nov 30, 2017
Type:
Certified Public Accountant

Eric T Ryan

Phone:
(212) 817-6089
License #:
110883 - Active
Category:
Legal Service Contract Sales Rep
Expiration Date:
Nov 17, 2017

Lawyers & Attorneys

Eric Ryan Photo 1

Eric Donovan Ryan, East Palo Alto CA - Lawyer

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Address:
DLA Piper US LLP
2000 University Ave, East Palo Alto, CA 94303
(650) 833-2118 (Office)
Licenses:
California - Active 1977
Education:
Bradley University
University of California at Berkeley, Boalt Hall School of Law
Specialties:
Tax - 50%
International Law - 50%
Eric Ryan Photo 2

Eric Ryan, East Palo Alto CA - Lawyer

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Office:
DLA Piper LLP
2000 University Ave., East Palo Alto, CA
Specialties:
Tax
International Tax
Tax Controversy
Health Care
ISLN:
901912563
Admitted:
1977
University:
Bradley University, B.A.
Law School:
University of California at Berkeley, J.D.

Public records

Vehicle Records

Eric Ryan

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Address:
2143 Montrose Ave UNIT 105, Montrose, CA 91020
VIN:
1G8MG35X67Y142668
Make:
SATURN
Model:
SKY
Year:
2007

Business Records

Name / Title
Company / Classification
Phones & Addresses
Eric D. Ryan
Attorney
Dla Piper
Legal Services
2000 University Avenue, Palo Alto, CA 94303
Eric Ryan
Owner
Eric Ryan
Personal Credit Institutions
29A San Carlos St., San Francisco, CA 94110
Eric Ryan
Manager
1731
Nonclassifiable Establishments
1728 Union St Ste 307, San Francisco, CA 94123
Eric Ryan
Inspector
Adept Fasteners, Inc
Hardware
28709 Industry Dr, Santa Clarita, CA 91355
Eric D Ryan
Attorney
Dla Piper
Legal Services
2000 University Ave, Palo Alto, CA 94303
Eric Ryan
President
Calhoun Learning Center Inc
Eric Ryan
President
The Calhoun School Inc
Eric Ryan
President
Noodle Head Inc
Eric D. Ryan
Attorney
Dla Piper
Legal Services
2000 University Avenue, Palo Alto, CA 94303
Eric Ryan
Owner
Eric Ryan
Personal Credit Institutions
29A San Carlos St., San Francisco, CA 94110
Eric Ryan
Manager
1731
Nonclassifiable Establishments
1728 Union St Ste 307, San Francisco, CA 94123
Eric Ryan
Inspector
Adept Fasteners, Inc
Hardware
28709 Industry Dr, Santa Clarita, CA 91355
Eric D Ryan
Attorney
Dla Piper
Legal Services
2000 University Ave, Palo Alto, CA 94303

Publications

Us Patents

Mram Array Having Reference Cell Structure And Circuitry That Reinforces Reference States By Induced Magnetic Field

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US Patent:
20200302983, Sep 24, 2020
Filed:
Mar 22, 2019
Appl. No.:
16/362329
Inventors:
- Fremont CA, US
Kadriye Deniz Bozdag - Sunnyvale CA, US
Eric Michael Ryan - Fremont CA, US
International Classification:
G11C 11/16
H01L 27/22
H01L 43/08
Abstract:
A magnetic memory device that includes magnetic read elements and magnetic reference cells. The magnetic reference cells include magnetic tunnel junction elements having the same construction as the magnetic read elements. The reference cells produce a reference signal that can be compared with a read signal from the magnetic read element to determine whether the read element is in a high or low resistance state. During creation of the reference signal, the current passes in such a way so that reference cells are forced to be in the right state while causing no disturbance to the reference cell. The reference cell includes magnetic tunnel junction elements and also includes circuitry configured to produce a magnetic field that biases the magnetic tunnel junction elements of the reference cell into a desired magnetic state to ensure that the desired magnetic state of the reference cell magnetic tunnel junction elements is maintained.

Patterned Silicide Structures And Methods Of Manufacture

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US Patent:
20200212296, Jul 2, 2020
Filed:
Dec 28, 2018
Appl. No.:
16/236275
Inventors:
- Freemont CA, US
Dafna Beery - Fremont CA, US
Marcin Gajek - Berkeley CA, US
Kadriye Deniz Bozdag - Sunnyvale CA, US
Eric Ryan - Fremont CA, US
Satoru Araki - San Jose CA, US
Andy Walker - Fremont CA, US
International Classification:
H01L 43/12
H01L 27/22
H01L 43/02
H01L 21/285
H01L 21/308
H01L 21/02
Abstract:
Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Method For Manufacturing A Data Recording System Utilizing Heterogeneous Magnetic Tunnel Junction Types In A Single Chip

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US Patent:
20200185601, Jun 11, 2020
Filed:
Dec 5, 2018
Appl. No.:
16/211167
Inventors:
- Fremont CA, US
Eric Michael Ryan - Fremont CA, US
International Classification:
H01L 43/12
H01L 43/02
Abstract:
A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.

Memory System Utilizing Heterogeneous Magnetic Tunnel Junction Types In A Single Chip

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US Patent:
20200143862, May 7, 2020
Filed:
Nov 1, 2018
Appl. No.:
16/178105
Inventors:
- Fremont CA, US
Eric Michael Ryan - Fremont CA, US
International Classification:
G11C 11/16
H01L 27/22
H01L 43/02
Abstract:
A magnetic data recording system utilizing different magnetic memory element types to optimize competing performance parameters in a common memory chip. The memory system includes a first memory portion which can be a main memory and which includes magnetic memory elements of a first type, and a second memory region which can be a temporary memory region and which includes magnetic memory elements of a second type. A memory controller can be provided for controlling the input and retrieval of data to and from the first and second memory elements. The second, memory region can be a scratchpad memory or could also be cache type memory. The first type of magnetic memory elements can be designed for high data retention, whereas the second type of magnetic memory elements can be designed for fast write speed (low latency) and low write power consumption.

High Density Mram Integration

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US Patent:
20200013827, Jan 9, 2020
Filed:
Dec 31, 2018
Appl. No.:
16/237171
Inventors:
- Fremont CA, US
Dafna Beery - Palo Alto CA, US
Marcin Gajek - Berkeley CA, US
Kadriye Deniz Bozdag - Sunnyvale CA, US
Eric Michael Ryan - Fremont CA, US
Satoru Araki - San Jose CA, US
Andrew J. Walker - Mountain View CA, US
International Classification:
H01L 27/22
G11C 11/16
H01L 43/12
H01L 43/10
H01L 43/08
H01L 43/02
Abstract:
A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSior CoSiand also causes the underlying amorphous silicon to crystallize.

High Density Mram Integration

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US Patent:
20200013828, Jan 9, 2020
Filed:
Dec 31, 2018
Appl. No.:
16/237194
Inventors:
- Fremont CA, US
Dafna Beery - Palo Alto CA, US
Marcin Gajek - Berkeley CA, US
Kadriye Deniz Bozdag - Sunnyvale CA, US
Eric Michael Ryan - Fremont CA, US
Satoru Araki - San Jose CA, US
Andrew J. Walker - Mountain View CA, US
International Classification:
H01L 27/22
H01L 43/12
H01L 43/10
H01L 43/08
H01L 43/02
G11C 11/16
Abstract:
A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSior CoSiand also causes the underlying amorphous silicon to crystallize.

Method For Manufacturing A Magnetic Memory Element Array Using High Angle Side Etch To Open Top Electrical Contact

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US Patent:
20190214553, Jul 11, 2019
Filed:
Jan 9, 2018
Appl. No.:
15/866394
Inventors:
- Fremont CA, US
Eric Michael Ryan - Fremont CA, US
Mustafa Pinarbasi - Morgan Hill CA, US
International Classification:
H01L 43/12
H01L 43/02
H01L 27/22
Abstract:
A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.

Perpendicular Magnetic Tunnel Junction Memory Cells Having Shared Source Contacts

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US Patent:
20190206463, Jul 4, 2019
Filed:
Dec 29, 2017
Appl. No.:
15/859040
Inventors:
- FREMONT CA, US
Dafna Beery - Palo Alto CA, US
Gian Sharma - Fremont CA, US
Marcin Gajek - Berkeley CA, US
Kadriye Deniz Bozdag - Sunnyvale CA, US
Girish Jagtiani - Santa Clara CA, US
Eric Michael Ryan - Fremont CA, US
Amitay Levi - Cupertino CA, US
Andrew J. Walker - Mountain View CA, US
International Classification:
G11C 11/16
Abstract:
A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.
Control profile
Eric G Ryan from Marina del Rey, CA, age ~47 Get Report