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Eric Johan Asperheim

from El Dorado Hills, CA
Age ~59
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Also known as:
Eric J Asperheim, Eric Asterheim, Eric M
Phone and address:
3535 Keswick Dr, Folsom, CA 95762
(916) 933-1661
Related to:
Muriel A HardinPeter Lopez, 55Faye Arnos, 81Francisco Corral, 62Kristin Oakes, 55Brandon White, 39
Connected to:
Steve J Aspery, 35Thomasa G Aspery, 68Anna Aspesi, 45Claire R Aspess, 44Wendy J Asphahani, 75Rolf G Asphaug, 66Jorge D Aspiazu, 51Carlos A Aspilcueta, 62Bienvenido L Aspili, 64Brenda L Aspillaga, 55

Eric Asperheim Phones & Addresses

  • 3535 Keswick Dr, El Dorado Hills, CA 95762 (916) 933-1661
  • 3565 Keswick Dr, El Dorado Hills, CA 95762
  • 1200 Creekside Dr, Folsom, CA 95630
  • Sacramento, CA
  • Plano, TX
  • Allen, TX
  • Austin, TX
  • Dallas, TX
  • El Dorado Hls, CA
  • 3535 Keswick Dr, El Dorado Hills, CA 95762 (916) 955-2354

Work

Company: Intel Position: Sr. staff design engineer

Education

Degree: MS School / High School: The University of Texas at Austin 1991 to 1992 Specialities: Computer Engineering

Skills

Gpu Design • Computer Architecture • Vlsi • Microprocessors • C++ • Semiconductors • Asic • Soc • Computer Hardware • Cpu Design • C# • Python • Verilog • Debugging • Perl • Rtl Design • Processors • Hardware Architecture • Tcl • Low Power Design

Emails

e***[email protected]

Industries

Computer Hardware

Resumes

Resumes

Eric Asperheim Photo 1

Principal Engineer - Intel

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Location:
Elm Grove, WI
Industry:
Computer Hardware
Work:
Intel
Sr. Staff Design Engineer
Education:
The University of Texas at Austin 1991 - 1992
MS, Computer Engineering Clemson University 1984 - 1988
BS, Electrical Engineering
Skills:
Gpu Design
Computer Architecture
Vlsi
Microprocessors
C++
Semiconductors
Asic
Soc
Computer Hardware
Cpu Design
C#
Python
Verilog
Debugging
Perl
Rtl Design
Processors
Hardware Architecture
Tcl
Low Power Design

Publications

Us Patents

Power Consumption Management For Communication Bus

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US Patent:
20200241622, Jul 30, 2020
Filed:
Feb 5, 2020
Appl. No.:
16/782791
Inventors:
- Santa Clara CA, US
Altug Koker - El Dorado Hills CA, US
Eric J. Hoekstra - Latrobe CA, US
Kiran C. Veernapu - Bangalore, IN
Prasoonkumar Surti - Folsom CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Eric J. Asperheim - El Dorado Hills CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Joydeep Ray - Folsom CA, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G06F 1/3225
G06F 1/3234
Abstract:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

Hybrid Low Power Homogenous Grapics Processing Units

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US Patent:
20200210238, Jul 2, 2020
Filed:
Dec 24, 2019
Appl. No.:
16/726341
Inventors:
- Santa Clara CA, US
Altug Koker - El Dorado Hills CA, US
Balaji Vembu - Folsom CA, US
Joydeep Ray - Folsom CA, US
Kamal Sinha - Rancho Cordova CA, US
Prasoonkumar Surti - Folsom CA, US
Kiran C. Veernapu - Bangalore, IN
Subramaniam Maiyuran - Gold River CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Eric J. Asperheim - El Dorado Hills CA, US
David Puffer - Tempe AZ, US
Wenyin Fu - Folsom CA, US
Nikos Kaburlasos - Lincoln CA, US
Bhushan M. Borole - Rancho Cordova CA, US
Josh B. Mastronarde - Sacramento CA, US
Linda L. Hurd - Cool CA, US
Travis T. Schluessler - Hillsboro OR, US
Tomasz Janczak - Gdansk, PL
Abhishek Venkatesh - Hillsboro OR, US
Kai Xiao - San Jose CA, US
Slawomir Grajewski - Gdansk, PL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/50
G06T 15/00
G06T 1/60
G06T 1/20
G06F 9/48
G06F 1/329
Abstract:
In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Dynamic Control Of Liquid Cooling Pumps To Provide Thermal Cooling Uniformity

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US Patent:
20190265765, Aug 29, 2019
Filed:
Feb 26, 2019
Appl. No.:
16/286166
Inventors:
- Santa Clara CA, US
Eric J. Asperheim - El Dorado Hills CA, US
Subramaniam Maiyuran - Gold River CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Joydeep Ray - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Prasoonkumar Surti - Folsom CA, US
Kiran C. Veernapu - Bangalore, IN
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/20
G05B 19/05
Abstract:
Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

Dynamic Control Of Liquid Cooling Pumps To Provide Thermal Cooling Uniformity

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US Patent:
20180307286, Oct 25, 2018
Filed:
Apr 21, 2017
Appl. No.:
15/493574
Inventors:
- Santa Clara CA, US
Eric J. Asperheim - El Dorado Hills CA, US
Subramaniam Maiyuran - Gold River CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Joydeep Ray - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Prasoonkumar Surti - Folsom CA, US
Kiran C. Veernapu - Bangalore, IN
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/20
G05B 19/05
Abstract:
Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

Adaptive Cache Sizing Per Workload

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US Patent:
20180300238, Oct 18, 2018
Filed:
Apr 17, 2017
Appl. No.:
15/488637
Inventors:
Balaji Vembu - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh B. Mastronarde - Sacramento CA, US
Nikos Kaburlasos - Lincoln CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Eric J. Asperheim - El Dorado Hills CA, US
Subramaniam Maiyuran - Gold River CA, US
Kiran C. Veernapu - Bangalore, IN
Pattabhiraman K - Bangalore, IN
Kamal Sinha - Rancho Cordova CA, US
Bhushan M. Borole - Rancho Cordova CA, US
Wenyin Fu - Folsom CA, US
Joydeep Ray - Folsom CA, US
Prasoonkumar Surti - Folsom CA, US
Eric J. Hoekstra - Latrobe CA, US
Travis T. Schluessler - Hillsboro OR, US
Linda L. Hurd - Cool CA, US
International Classification:
G06F 12/06
Abstract:
Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

Dual Path Sequential Element To Reduce Toggles In Data Path

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US Patent:
20180293780, Oct 11, 2018
Filed:
Apr 10, 2017
Appl. No.:
15/483580
Inventors:
- Santa Clara CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Kiran C. Veernapu - Bangalore, IN
Eric J. Asperheim - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Balaji Vembu - Folsom CA, US
Joydeep Ray - Folsom CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 15/00
G06F 1/32
Abstract:
Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

Power Consumption Management For Communication Bus

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US Patent:
20180284873, Oct 4, 2018
Filed:
Apr 1, 2017
Appl. No.:
15/477042
Inventors:
- Santa Clara CA, US
Altug Koker - El Dorado Hills CA, US
Eric J. Hoekstra - Latrobe CA, US
Kiran C. Veernapu - Bangalore, IN
Prasoonkumar Surti - Folsom CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Eric J. Asperheim - El Dorado Hills CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Joydeep Ray - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
Abstract:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

Hybrid Low Power Homogenous Grapics Processing Units

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US Patent:
20180285158, Oct 4, 2018
Filed:
Apr 1, 2017
Appl. No.:
15/477026
Inventors:
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Balaji Vembu - Folsom CA, US
Joydeep Ray - Folsom CA, US
Kamal Sinha - Rancho Cordova CA, US
Prasoonkumar Surti - Folsom CA, US
Kiran C. Veernapu - Bangalore, IN
Subramaniam Maiyuran - Gold River CA, US
Sanjeev S. Jahagirdar - Folsom CA, US
Eric J. Asperheim - El Dorado Hills CA, US
David Puffer - Tempe AZ, US
Wenyin Fu - Folsom CA, US
Nikos Kaburlasos - Lincoln CA, US
Bhushan M. Borole - Rancho Cordova CA, US
Josh B. Mastronarde - Sacramento CA, US
Linda L. Hurd - Cool CA, US
Travis T. Schluessler - Hillsboro OR, US
Tomasz Janczak - Gdansk, PL
Abhishek Venkatesh - Hillsboro OR, US
Kai Xiao - Santa Clara CA, US
Slawomir Grajewski - Gdansk, PL
International Classification:
G06F 9/50
G06T 1/60
G06T 1/20
G06T 15/00
G06F 9/48
G06F 1/32
Abstract:
In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
Control profile
Eric Johan Asperheim from El Dorado Hills, CA, age ~59 Get Report