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Eric C Aardoom

from Pawtucket, RI
Age ~61
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Also known as:
Eric D Aardoom, Eric Aardon, Adoom A Eric, Aard M Eric, O Eric
Phone and address:
10 Kenilworth Way, Pawtucket, RI 02860
Connected to:
Helen E Aardsma, 70Jason R Aardsma, 38Aishwarya Aare, 34Maysie M Aarestad, 80Alan W Aarhus, 72Beth M Aarhus, 52Michelle A Aarhus, 50Victoria S Aarhus, 65Jens P Aarnaes, 67Turi K Aarnes, 51

Eric Aardoom Phones & Addresses

  • 10 Kenilworth Way, Pawtucket, RI 02860
  • Framingham, MA
  • Watertown, MA
  • Cranston, RI
  • West Roxbury, MA

Work

Company: Marvell semiconductor Jul 2018 Position: Senior lead

Education

School / High School: Industrial Design Engineering, Tu Delft 1989 Specialities: Avionics, Communication

Skills

Soc • Asic • Embedded Systems • Digital Signal Processors • Functional Verification • Simulations • Verilog • Systemverilog • Signal Processing • Vlsi • Computer Architecture • Wireless • Fpga • Integrated Circuit Design • Eda • Debugging • Vhdl • Rtl Design • Dft • C++ • Arm • Matlab • System Design • Low Power Design • Mixed Signal • Uvm • Timing Closure • Microprocessors • Logic Synthesis • Vmm • Dsp • Hardware Design • Static Timing Analysis • Formal Verification • Tcl • Modems • Systemc • Modelsim • Nc Verilog • Vcs • Ovm • Umts • Td Scdma • Gps • Python • Cmos • C • Perl • Electronics • Lte • Ic • Esl

Industries

Semiconductors

Resumes

Resumes

Eric Aardoom Photo 1

Senior Lead

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Location:
10 Kenilworth Way, Pawtucket, RI 02860
Industry:
Semiconductors
Work:
Marvell Semiconductor
Senior Lead
Marvell Semiconductor
Staff Engineer
Cavium Inc
Consulting Engineer
Qualcomm Jun 2008 - Aug 2012
Senior Staff Engineer
Mediatek Jan 2008 - Jun 2008
Chip Lead, 3G Digital Baseband
Education:
Industrial Design Engineering, Tu Delft 1989
Skills:
Soc
Asic
Embedded Systems
Digital Signal Processors
Functional Verification
Simulations
Verilog
Systemverilog
Signal Processing
Vlsi
Computer Architecture
Wireless
Fpga
Integrated Circuit Design
Eda
Debugging
Vhdl
Rtl Design
Dft
C++
Arm
Matlab
System Design
Low Power Design
Mixed Signal
Uvm
Timing Closure
Microprocessors
Logic Synthesis
Vmm
Dsp
Hardware Design
Static Timing Analysis
Formal Verification
Tcl
Modems
Systemc
Modelsim
Nc Verilog
Vcs
Ovm
Umts
Td Scdma
Gps
Python
Cmos
C
Perl
Electronics
Lte
Ic
Esl

Publications

Us Patents

Multi-Mode Bit Rate Processor

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US Patent:
8149702, Apr 3, 2012
Filed:
Aug 27, 2008
Appl. No.:
12/199640
Inventors:
Deepak Mathew - Wilmington MA, US
Eric Aardoom - Framingham MA, US
Timothy Perrin Fisher-Jeffes - Cambridge MA, US
David Stephen Ivory - Cambridgeshire, GB
Carsten Aagaard Pedersen - Belmont MA, US
Aiguo Yan - Andover MA, US
Assignee:
MediaTek Inc. - Hsin-Chu
International Classification:
H04J 1/16
US Classification:
3702301, 370428
Abstract:
An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Re-Quantization In Downlink Receiver Bit Rate Processor

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US Patent:
8358987, Jan 22, 2013
Filed:
Sep 28, 2006
Appl. No.:
11/529071
Inventors:
Deepak Mathew - Wilmington MA, US
Aiguo Yan - North Andover MA, US
Krishnan Vishwanathan - Newburgh NY, US
Eric Aardoom - Framingham MA, US
Timothy Fisher-Jeffes - Cambridge, GB
Assignee:
MediaTek Inc. - Hsin-Chu
International Classification:
H04B 1/18
US Classification:
4551871, 455423, 4555521, 370342, 370232
Abstract:
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

Interface Between Chip Rate Processing And Bit Rate Processing In Wireless Downlink Receiver

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US Patent:
8358988, Jan 22, 2013
Filed:
Sep 28, 2006
Appl. No.:
11/529146
Inventors:
Lidwine Martinot - Cottenham, GB
Deepak Mathew - Wilmington MA, US
Krishnan Vishwanathan - Newburgh NY, US
Eric Aardoom - Framingham MA, US
Aiguo Yan - North Andover MA, US
Timothy Fisher-Jeffes - Cambridge, GB
Assignee:
MediaTek Inc. - Hsin-Chu
International Classification:
H04B 1/18
US Classification:
4551871, 455423, 4555521, 370342, 370320, 370335, 370441
Abstract:
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

Transport Channel Buffer Organization In Downlink Receiver Bit Rate Processor

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US Patent:
20080080444, Apr 3, 2008
Filed:
Sep 28, 2006
Appl. No.:
11/529182
Inventors:
Timothy Fisher-Jeffes - Cambridge, GB
Deepak Mathew - Wilmington MA, US
Krishnan Vishwanathan - Newburgh NY, US
Eric Aardoom - Framingham MA, US
Aiguo Yan - North Andover MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H04B 7/216
US Classification:
370342
Abstract:
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.

Architecture For Downlink Receiver Bit Rate Processor

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US Patent:
20080080542, Apr 3, 2008
Filed:
Sep 28, 2006
Appl. No.:
11/529148
Inventors:
Krishnan Vishwanathan - Newburgh NY, US
Deepak Mathew - Wilmington MA, US
Eric Aardoom - Framingham MA, US
Lidwine Martinot - Cottenham, GB
Aiguo Yan - North Andover MA, US
Timothy Fisher-Jeffes - Cambrige, GB
Paul D. Krivacek - North Andover MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H04L 12/56
US Classification:
370412
Abstract:
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
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Eric C Aardoom from Pawtucket, RI, age ~61 Get Report