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Erdinc Ozturk

from Worcester, MA
Age ~42
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Related to:
Celal Ozturk, 40
Connected to:
Ayla Ozturk, 55Binnur Ozturk, 71Ceren OzturkEmine Ozturk, 38Gulsen Ozturk, 41Hafsa Ozturk, 42Haluk J Ozturk, 62Melissa K Ozturk, 68Misty A Ozturk, 54Nihat H Ozturk, 56

Erdinc Ozturk Phones & Addresses

  • Worcester, MA
  • San Diego, CA
  • Novi, MI
  • Marlborough, MA
  • Cambridge, MA
  • Hillsboro, OR
  • Wakefield, RI

Work

Company: Intel corporation May 2008 Position: Graduate technical intern

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Worcester Polytechnic Institute 2005 to 2008 Specialities: Electrical Engineering

Industries

Computer Hardware

Resumes

Resumes

Erdinc Ozturk Photo 1

Graduate Technical Intern

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Location:
Worcester, MA
Industry:
Computer Hardware
Work:
Intel Corporation
Graduate Technical Intern
Worcester Polytechnic Institute
Research Assistant
Worcester Polytechnic Institute Aug 2003 - May 2004
Teaching Assistant
Education:
Worcester Polytechnic Institute 2005 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering Worcester Polytechnic Institute 2003 - 2005
Master of Science, Masters, Electrical Engineering Sabanci University 1999 - 2003
Bachelors

Publications

Us Patents

Method For Simultaneous Modular Exponentiations

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US Patent:
7925011, Apr 12, 2011
Filed:
Dec 14, 2006
Appl. No.:
11/610919
Inventors:
Vinodh Gopal - Westboro MA, US
Erdinc Ozturk - Worcester MA, US
Kaan Yuksel - Worcester MA, US
Gunnar Gaubatz - Worcester MA, US
Wajdi Feghali - Boston MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/00
US Classification:
380 30, 380 28, 380 44, 380 45, 380277, 709228, 713100
Abstract:
The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y).

Factoring Based Modular Exponentiation

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US Patent:
7961877, Jun 14, 2011
Filed:
Dec 14, 2006
Appl. No.:
11/610886
Inventors:
Vinodh Gopal - Westboro MA, US
Erdinc Ozturk - Worcester MA, US
Matt Bace - North Andover MA, US
Wajdi Feghali - Boston MA, US
Robert P. Ottavi - Brookline MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/30
H04L 9/28
H04L 9/00
G06G 7/16
US Classification:
380 30, 380 28, 380 44, 709250, 713192
Abstract:
The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Scale-Invariant Barrett Reduction For Elliptic-Curve Cyrptography

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US Patent:
7978846, Jul 12, 2011
Filed:
Jun 30, 2007
Appl. No.:
11/772169
Inventors:
Erdinc Ozturk - Worcester MA, US
Vinodh Gopal - Westboro MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04K 1/00
H04L 9/00
H04L 9/28
H04L 9/30
G06F 7/72
US Classification:
380 30, 380 28, 380 46, 708490, 708491, 708492, 708518, 708523, 708525
Abstract:
The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N.

Efficient Elliptic-Curve Cryptography Based On Primality Of The Order Of The Ecc-Group

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US Patent:
7986779, Jul 26, 2011
Filed:
Jun 30, 2007
Appl. No.:
11/772170
Inventors:
Erdinc Ozturk - Worcester MA, US
Vinodh Gopal - Westboro MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04K 1/00
H04L 9/00
H04L 9/28
G06F 7/72
US Classification:
380 30, 380 28, 380 46, 708490, 708491, 708492, 708518, 708523, 708525
Abstract:
Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.

Modulus Scaling For Elliptic-Curve Cryptography

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US Patent:
8005210, Aug 23, 2011
Filed:
Jun 30, 2007
Appl. No.:
11/772165
Inventors:
Erdinc Ozturk - Worcester MA, US
Vinodh Gopal - Westboro MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04K 1/00
H04L 9/00
H04L 9/28
G06F 7/72
US Classification:
380 30, 380 28, 380 46, 708490, 708491, 708492, 708518, 708523, 708525
Abstract:
Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.

Unified Integer/Galois Field (2M) Multiplier Architecture For Elliptic-Curve Crytpography

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US Patent:
8271570, Sep 18, 2012
Filed:
Jun 30, 2007
Appl. No.:
11/772166
Inventors:
Vinodh Gopal - Westboro MA, US
Erdinc Ozturk - Worcester MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/00
US Classification:
708492
Abstract:
A unified integer/Galois-Field 2multiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The multiply operations may be performed on prime fields and different composite binary fields in independent multipliers in an interleaved fashion.

Residue Generation

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US Patent:
8312363, Nov 13, 2012
Filed:
Dec 16, 2008
Appl. No.:
12/336029
Inventors:
Vinodh Gopal - Westborough MA, US
Erdinc Ozturk - Worcester MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi Feghali - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714808, 714807, 708531, 708532
Abstract:
In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

Efficient Advanced Encryption Standard (Aes) Datapath Using Hybrid Rijndael S-Box

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US Patent:
8346839, Jan 1, 2013
Filed:
Mar 30, 2007
Appl. No.:
11/731159
Inventors:
Erdinc Ozturk - Worcester MA, US
Vinodh Gopal - Westboro MA, US
Gilbert Wolrich - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
Kirk S. Yap - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/52
US Classification:
708620
Abstract:
The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
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Erdinc Ozturk from Worcester, MA, age ~42 Get Report