Enrique Ferrer

54836913, Jan 9, 1996

Jul 14, 1994

8/275088

Joseph P. Heck - Ft. Lauderdale FL
Enrique Ferrer - Miami FL

Motorola, Inc. - Schaumburg IL

H04B 116

4552342

A receiver automatic gain control (AGC) circuit includes a first adjustable gain control amplifier (158) which is responsive to a gain control signal (156). The AGC circuit further includes a second adjustable gain control amplifier (114) and a control circuit (116) which receives the gain control signal (156) and provides a modified gain control signal or VCNTRL (152) to the second adjustable control amplifier (114). The control circuit (116) also limits the amount of gain control applied to adjustable gain control amplifiers (114 and 118) when the gain control signal (156) reaches a certain predetermined level. This provides for all further gain reduction to occur at the first adjustable gain control amplifier (158) and thereby reduce the chances for distortion under high input signal conditions.

49202855, Apr 24, 1990

Nov 21, 1988

7/274167

Edward T. Clark - Plantation FL
Enrique Ferrer - Miami FL

Motorola, Inc. - Schaumburg IL

H03K 17687
G06G 728
H02J 1700

307571

An RF signal is transformed (12 and 12') to increase its current component, while reducing its voltage component below the voltage that would damage a GaAs switching device (16 or 16'). The current and voltage transformation are selected so that the power of the RF signal remains substantially constant. Subsequent to the GaAs switching device, the signal is converted (24 and 24') to increase the voltage component while decreasing its current component to substantially recreate the original RF signal.

49873920, Jan 22, 1991

Oct 17, 1988

7/258934

Edward T. Clark - Plantation FL
Enrique Ferrer - Miami FL

Motorola, Inc. - Schaumburg IL

H01P 115

333103

An electronic switch uses GaAs transistors to switch signals that have peak-to-peak voltage swings that exceed the breakdown voltage of the transistors. A two port impedance transformer (Z1) has a high input impedance and a low output impedance to transform a high voltage input signal (at T1) to a corresponding output signal having lower voltage, but higher current. This transformed signal is coupled to the second port of a three port impedance transformer (Z2) through a first GaAs transistor switch (Q1). A half wave rectifier circuit (D1, R7, R8 and C3) generates a negative DC voltage from the input signal (at T1), thereby eliminating the requirement for a separate bias voltage supply. A bipolar transistor switch selectively couples this negative bias voltage to the gate of the first GaAs transistor (Q1). The second port of the three port impedance transformer (Z2) has a lower impedance than either the first or third ports.

47136316, Dec 15, 1987

Jan 6, 1986

6/816589

Ralph T. Enderby - Sunrise FL
Enrique Ferrer - Miami FL
Wayne P. Shepherd - Sunrise FL

Motorola Inc. - Schaumburg IL

H03B 508
H03H 512
H03L 718

331 36C

A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.

48855502, Dec 5, 1989

Dec 1, 1988

7/278381

Enrique Ferrer - Miami FL

Motorola, Inc. - Schaumburg IL

H03F 368
H03F 316

330301

A single input, differential output amplifier (50) includes two Gallium Arsenide field effect transistors: one arranged to form a common gate amplifier (55) to provide a non-inventing output (60), and the other arranged to form a common source (65) amplifier to provide an inverting output (61). The input of each FET is connected to receive an input signal simultaneously thereby minimizing phase delay in the differential output signals. In another aspect of the invention, the non-inverting stage (55) is incorporated into the biasing network for the inverting ampllifier (65).

63170647, Nov 13, 2001

Feb 29, 2000

9/515834

Enrique Ferrer - Miami FL
James C. Goatley - Sunrise FL
Keith A. Tilley - Round Rock TX
Raul Salvi - Miami FL

Motorola, Inc. - Schaumburg IL

H03M 110

341118

A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (100), a digital slow averaging scheme (200) and an analog integration (50) scheme are provided. A controller (160) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.

46865284, Aug 11, 1987

Mar 26, 1986

6/843876

Enrique Ferrer - Miami FL
Charles M. Schlosser - Coral Springs FL

Motorola, Inc. - Schaumburg IL

G08B 522

34082544

In a multiple state data signal, a first and second state are equated to logic states while a third state is designated as a read state. The read state and one of the two logic states are alternately generated so that each logic state is immediately preceeded by a read signal which may be utilized to tell the peripheral that a valid bit of data follows.

61155896, Sep 5, 2000

Apr 29, 1997

8/841242

Enrique Ferrer - Miami FL
Charles R. Ruelke - Plantation FL
Andrew J. Webster - Basingstoke, GB
Kenneth A. Hansen - Round Rock TX
Rajesh H. Zele - Plantation FL
Kevin B. Traylor - Austin TX

Motorola, Inc. - Schaumburg IL

H04B 106
H04H 500
G10L 2100

4552491

A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.