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Emil I Gizdarski

from Cupertino, CA
Age ~66
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Also known as:
Emil Gazdarski, Emil I
Phone and address:
20800 Homestead Rd, Cupertino, CA 95014
(408) 973-8446
Related to:
Konstantin E Gizdarski, 30
Connected to:
Jerry M Gizdich, 104Joseph A Gize, 49Karen A Gize, 57Brittany F Gizelbach, 29Greg G Gizelbach, 55Richard W Gizelbach, 76Alexandra Gizhitsa, 36Nancy A Gizi, 44Nada J Gizicki, 78Amy L Gizienski, 45

Emil Gizdarski Phones & Addresses

  • 20800 Homestead Rd, Cupertino, CA 95014 (408) 973-8446
  • Santa Clara, CA
  • Mountain View, CA
  • 3770 Flora Vista Ave APT 501, Santa Clara, CA 95051 (408) 824-7930

Work

Company: Synopsys Aug 1, 2014 Position: Principal engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Technical University of Sofia 1987 to 1989 Specialities: Computer Science

Skills

Debugging • Eda • Testing • Verilog • Vlsi • Dft • Atpg • Asic • Algorithms • Soc • C++ • Tcl • C • Embedded Systems • Rtl Design • Simulations • Computer Architecture • Vhdl • Microprocessors • Static Timing Analysis • Semiconductors • Fpga • Integrated Circuit Design • Ic • Formal Verification • Computer Science • Perl • Jtag • Cmos • Hardware Architecture • Digital Signal Processors • Embedded Software • Modelsim • Logic Design • Mixed Signal • Field Programmable Gate Arrays • Integrated Circuits • System on A Chip • Very Large Scale Integration • Application Specific Integrated Circuits • Hardware Diagnostics

Languages

English

Emails

e***[email protected]

Industries

Computer Software

Resumes

Resumes

Emil Gizdarski Photo 1

Principal Engineer

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Location:
20800 Homestead Rd, Cupertino, CA 95014
Industry:
Computer Software
Work:
Synopsys
Principal Engineer
Synopsys Oct 2001 - Aug 2014
Senior Staff Engineer
Nara Institute of Science and Technology Dec 1999 - Sep 2001
Jsps Postdoc Fellow
Univeristy of Rousse 1989 - 1999
Assistant Professor
Education:
Technical University of Sofia 1987 - 1989
Doctorates, Doctor of Philosophy, Computer Science University of Ruse 1981 - 1987
Master of Science, Masters, Computer Engineering
Skills:
Debugging
Eda
Testing
Verilog
Vlsi
Dft
Atpg
Asic
Algorithms
Soc
C++
Tcl
C
Embedded Systems
Rtl Design
Simulations
Computer Architecture
Vhdl
Microprocessors
Static Timing Analysis
Semiconductors
Fpga
Integrated Circuit Design
Ic
Formal Verification
Computer Science
Perl
Jtag
Cmos
Hardware Architecture
Digital Signal Processors
Embedded Software
Modelsim
Logic Design
Mixed Signal
Field Programmable Gate Arrays
Integrated Circuits
System on A Chip
Very Large Scale Integration
Application Specific Integrated Circuits
Hardware Diagnostics
Languages:
English

Publications

Us Patents

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7418640, Aug 26, 2008
Filed:
May 28, 2004
Appl. No.:
10/856105
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
G06F 11/00
US Classification:
714726, 714 37
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7596733, Sep 29, 2009
Filed:
Jul 23, 2008
Appl. No.:
12/178517
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714726, 714732
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7743299, Jun 22, 2010
Filed:
Jul 23, 2008
Appl. No.:
12/178504
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714729
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7774663, Aug 10, 2010
Filed:
Jul 9, 2009
Appl. No.:
12/500296
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714726, 714724, 714729
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7836367, Nov 16, 2010
Filed:
Aug 11, 2009
Appl. No.:
12/539538
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714726, 714729
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7836368, Nov 16, 2010
Filed:
Aug 24, 2009
Appl. No.:
12/546595
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714726, 714729
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Method And Apparatus For Synthesis Of Augmented Multimode Compactors

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US Patent:
7882409, Feb 1, 2011
Filed:
Oct 31, 2008
Appl. No.:
12/263198
Inventors:
Emil Gizdarski - Santa Clara CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714729, 714 25, 714 30, 714724, 714726, 714727, 714732, 714741
Abstract:
Proposed are methods and apparatuses for synthesis of a new class of compressors called augmented multimode compactors, capable of achieving a flexible trade-off between compaction ratio, observability, control data volume and diagnostic properties in the presence of a large number of unknown values. The augmented multimode compactors reduce and/or completely avoid the X-masking effect in the compacted test responses. In addition, a requirement for constructing compactors is that any single error in the test response produces a unique erroneous signature within S consecutive shift cycles where the erroneous signature is calculated as a difference between the faulty signature and the fault-free signature.

Dynamically Reconfigurable Shared Scan-In Test Architecture

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US Patent:
7900105, Mar 1, 2011
Filed:
May 12, 2010
Appl. No.:
12/779018
Inventors:
Rohit Kapur - Cupertino CA, US
Nodari Sitchinava - San Mateo CA, US
Samitha Samaranayake - San Mateo CA, US
Emil Gizdarski - Santa Clara CA, US
Frederic J. Neuveux - Meylan, FR
Suryanarayana Duggirala - San Jose CA, US
Thomas W. Williams - Boulder CO, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
US Classification:
714726, 714729
Abstract:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
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Emil I Gizdarski from Cupertino, CA, age ~66 Get Report