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Emery P Gasparek

from Memphis, NY
Age ~63
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Also known as:
Emery J Gasparek, Jr Emery Gasparek, Emery P Gasper, Aarel G Emery
Phone and address:
2024 Canal Rd, Memphis, NY 13112
(315) 487-1869
Related to:
Jennifer L Gasparek, 33Betty Gasparek, 88Matthew Gasparek, 31Jodi Gasparek, 59
Connected to:
Altagrace A Gaspard, 47Andy L Gaspard, 35Casey J Gaspard, 45Catheleen Gaspard, 52Catherine L Gaspard, 46Christopher S Gaspare, 44Chuck Gaspard, 56Courtney Gaspard, 43Cristina Gasparetto, 64Diana L Gaspard, 69

Emery Gasparek Phones & Addresses

  • 2024 Canal Rd, Memphis, NY 13112 (315) 487-1869 (315) 689-3255
  • Trenton, MI
  • 132 Bennett Rd, Camillus, NY 13031 (315) 487-6840 (607) 487-6840
  • Hammond, NY
  • 200 Inwood Dr, Syracuse, NY 13219 (315) 487-1869

Work

Company: Veterans administation May 2018 Position: General engineer

Education

Degree: Bachelor of Science In Mechanical Engineering, Bachelors School / High School: Clarkson University

Skills

Automotive

Industries

Automotive

Resumes

Resumes

Emery Gasparek Photo 1

General Engineer

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Location:
Syracuse, NY
Industry:
Automotive
Work:
Veterans Administation
General Engineer
Fca Fiat Chrysler Automobiles
Facilities Engineer
Education:
Clarkson University
Bachelor of Science In Mechanical Engineering, Bachelors
Skills:
Automotive

Business Records

Name / Title
Company / Classification
Phones & Addresses
Emery P. Gasparek
Principal
Emery P Gasparek Jr
Business Services at Non-Commercial Site
2024 Canal Rd, Memphis, NY 13112

Publications

Us Patents

Matrix Multiplier

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US Patent:
41617851, Jul 17, 1979
Filed:
Nov 17, 1977
Appl. No.:
5/852501
Inventors:
Emery P. Gasparek - Camillus NY
Assignee:
General Electric Company - Syracuse NY
International Classification:
G06G 719
G06G 716
H03K 5159
US Classification:
364827
Abstract:
A matrix multiplier is described for multiplying sampled data in analog format by a matrix of stored values also in analog format and of positive or negative sign. The analog input quantity in the form of an electrical charge is applied to individual circuit elements making up the matrix. Each circuit element contains a capacitive storage means for encoding a stored value. An output term proportional to the product of the applied charge and the capacitance is produced in each circuit element. The input quantities are applied to the circuit elements in parallel by rows, and the output quantities are derived in parallel by columns to achieve matrix multiplication. In one form, the multiplier is a matrix of one stage charged coupled devices, each using a partitioned electrode storage site with the partitioning varying from element to element. The invention leads to a simple and high speed design. The invention is applicable to the computation of the Discrete Fourier Transformation.
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Emery P Gasparek from Memphis, NY, age ~63 Get Report