Elizabeth J Schlapp

6535218, Mar 18, 2003

Oct 1, 1998

09/164858

Elizabeth J. Schlapp - San Jose CA

Mitsubishi Electric Electronics USA, Inc. - Cypress CA

G06F 1516

345545, 345555, 345557

A frame buffer memory is disclosed which provides accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system. One embodiment of the disclosed memory comprises a memory array, a pixel buffer, a plurality of pixel arithmetic-logic units, an input data formatter, an output data formatter, a read data formatter, a write data formatter and an address and control input bus.

6559851, May 6, 2003

Mar 8, 1999

09/264281

Elizabeth J. Schlapp - San Jose CA

Mitsubishi Electric Electronics USA, Inc. - Cypress CA

G09G 539

345531, 345501, 345530, 345538

Methods for operating a graphics system which employs one or more frame buffer memory devices are disclosed which methods provide for accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system One disclosed operation is a method for compressing data to be transmitted from a controller to the memory device and then decompressing the data within the memory device once it has been transmitted and received.

6661421, Dec 9, 2003

Mar 8, 1999

09/264261

Elizabeth J. Schlapp - San Jose CA

Mitsubishi Electric Electronics USA, Inc. - Cypress CA

G06T 160

345530, 345501, 345531, 345538, 345546, 382232, 382233

Methods for operating a frame buffer memory device are disclosed which provide for accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system One disclosed operation is a method for compressing data to be transmitted from a controller to the memory device and then decompressing the data within the memory device once it has been transmitted and received.

6504550, Jan 7, 2003

Oct 1, 1998

09/164866

Elizabeth J. Schlapp - San Jose CA

Mitsubishi Electric Electronics USA, Inc. - Cypress CA

G06F 1516

345545, 345555, 345557, 345503

A graphics processing system which employs one or more frame buffer memory devices is disclosed which system provides accelerated rendering of two-dimensional and three-dimensional images. One embodiment of the disclosed system comprises a rendering controller, an interface, a frame buffer memory, a rendering bus and an address and control bus.