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Eliot Broadbent Phones & Addresses

  • 10950 Avocet Ct, Beaverton, OR 97007 (503) 277-3466
  • San Jose, CA
  • Albany, OR
  • Norman, OK
  • Orem, UT
  • Los Angeles, CA
  • Provo, UT
  • 10950 SW Avocet Ct, Beaverton, OR 97007 (503) 720-3264

Work

Position: Administration/Managerial

Education

Degree: High school graduate or higher

Emails

Business Records

Name / Title
Company / Classification
Phones & Addresses
Eliot Broadbent
Principal
TRADE4GAIN LLC
Business Services at Non-Commercial Site
10950 SW Avocet Ct, Beaverton, OR 97007

Publications

Us Patents

Passivation Of Copper In Dual Damascene Metalization

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US Patent:
6554914, Apr 29, 2003
Filed:
Feb 2, 2001
Appl. No.:
09/776704
Inventors:
Robert T. Rozbicki - San Jose CA
Ronald Allan Powell - San Carlos CA
Erich Klawuhn - San Jose CA
Michal Danek - Sunnyvale CA
Karl B. Levy - Los Altos CA
Jonathan David Reid - Sherwood OR
Mukul Khosla - San Jose CA
Eliot K. Broadbent - Beaverton OR
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C23C 824
US Classification:
148238, 148282
Abstract:
The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

Method And Apparatus For Uniform Electropolishing Of Damascene Ic Structures By Selective Agitation

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US Patent:
6709565, Mar 23, 2004
Filed:
Sep 28, 2001
Appl. No.:
09/967075
Inventors:
Steven T. Mayer - Lake Oswego OR
Robert J. Contolini - Lake Oswego OR
Eliot K. Broadbent - Beaverton OR
John S. Drewery - Alameda CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
B23H 1100
US Classification:
205640, 205662, 205663, 205674, 205672, 205682, 205686
Abstract:
The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.

Method For Manufacturing An Electrical Interconnection By Selective Tungsten Deposition

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US Patent:
45172250, May 14, 1985
Filed:
May 2, 1983
Appl. No.:
6/490381
Inventors:
Eliot K. Broadbent - San Jose CA
Assignee:
Signetics Corporation - Sunnyvale CA
International Classification:
H01L 21285
H01L 2188
US Classification:
427 89
Abstract:
A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Method Of Forming An Aluminum Conductor With Highly Oriented Grain Structure

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US Patent:
49768093, Dec 11, 1990
Filed:
Dec 18, 1989
Appl. No.:
7/452860
Inventors:
Eliot K. Broadbent - San Jose CA
Assignee:
North American Philips Corp, Signetics Division - Sunnyvale CA
International Classification:
B44C 122
C23F 102
C03C 1500
C03C 2506
US Classification:
156643
Abstract:
Aluminum alloy polycrystalline conductors having reduced electro-migration tendencies are formed in a semiconductor device by applying a thin film of aluminum or aluminum alloy to an array of shallow holes provided in a dielectric layer the array being patterned according to a desired interconnection pattern. A thin film of aluminum or aluminum alloy is then scanned with a laser beam sufficient to melt the film and cause it to planarize. An oriented crystal structure is formed with grain boundaries being aligned orthogonally to the rows and column of the hole pattern. A photoresist mask is then aligned with the resultant crystal structure in a manner such that boundaries extend substantially only in a direction across the width of the desired conductor lines. The aluminum which is present in the crystal structure outside the desired conductor line is then removed by plasma etching through the mask.

Method Of Electroplating Semiconductor Wafer Using Variable Currents And Mass Transfer To Obtain Uniform Plated Layer

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US Patent:
6162344, Dec 19, 2000
Filed:
Sep 9, 1999
Appl. No.:
9/393226
Inventors:
Jonathan D. Reid - Sherwood OR
Robert J. Contolini - Lake Oswego OR
Edward C. Opocensky - Aloah OR
Evan E. Patton - Portland OR
Eliot K. Broadbent - Beaverton OR
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C25D 712
C25D 500
US Classification:
205157
Abstract:
In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.

Gas-Based Backside Protection During Substrate Processing

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US Patent:
52307417, Jul 27, 1993
Filed:
Jul 16, 1990
Appl. No.:
7/554225
Inventors:
Everhardus P. van de Ven - Cupertino CA
Eliot K. Broadbent - San Jose CA
Jeffrey C. Benzing - San Jose CA
Barry L. Chin - Sunnyvale CA
Christopher W. Burkhart - San Jose CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 2168
US Classification:
118728
Abstract:
A suitable inert gas such as argon or a mixture of inert and reactive gases such as argon and hydrogen is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals, metal nitrides and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. A vacuum chuck including a number of radial and circular vacuum grooves in the top surface of the platen is provided for holding the wafer in place. A platen heater is provided under the platen. Backside gas is heated in and about the bottom of the platen, and introduced through a circular groove in the peripheral region outside of the outermost vacuum groove of the vacuum chuck. Backside gas pressure is maintained in this peripheral region at a level greater than the CVD chamber pressure. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gas from contacting the wafer backside.

Sweeping Method And Magnet Track Apparatus For Magnetron Sputtering

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US Patent:
51887177, Feb 23, 1993
Filed:
Sep 12, 1991
Appl. No.:
7/760027
Inventors:
Eliot K. Broadbent - San Jose CA
Kenneth C. Miller - Mountain View CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C23C 1434
US Classification:
20419212
Abstract:
A magnetism sputtering apparatus is provided with a movable magnetic track which is a closed curve essentially in the shape of a kidney bean, the closed curve being generated in part by a spiral curve. The magnet track is positioned behind the target of the sputtering apparatus, and it is simultaneously rotated about a center of rotation and caused to oscillate substantially radially with respect to said center of rotation. The combined rotational and oscillatory motion provides a substantially uniform magnetic flux over a major annular portion of the target while ensuring that some degree of sputtering occurs in all regions of the target, including regions near the center and periphery of the target. This arrangement has been found suitable for providing a highly uniform deposition of target material on large diameter substrates.

Method For Preventing Substrate Backside Deposition During A Chemical Vapor Deposition Operation

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US Patent:
56794053, Oct 21, 1997
Filed:
Jul 24, 1995
Appl. No.:
8/506246
Inventors:
Michael E. Thomas - Milpitas CA
Everhardus P. van de Van - Cupertino CA
Eliot K. Broadbent - San Jose CA
Assignee:
National Semiconductor Corp. - Santa Clara CA
Novellus Systems, Inc. - San Jose CA
International Classification:
C23C 1604
C23C 1652
US Classification:
4272481
Abstract:
A suitable inert thermal gas such as argon is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. The platen has a circular depression for receiving a wafer, and an annular groove provided in the floor of the depression, near the wall thereof. Heated and pressurized backside gas is introduced into the groove so that the wafer is maintained in a position above the floor of the depression but still within it. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gases from contacting the wafer backside. The backside gas is also used for levitating the wafer in a transfer region above the platen, so that the wafer can be transported to or from the platen with a suitable wafer transfer mechanism. One suitable transfer mechanism is a multi-armed spindle, the arms being respective pairs of tines.

Isbn (Books And Publications)

Tungsten and Other Refractory Metals for Vlsi Applications II: Proceedings

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Author

Eliot K. Broadbent

ISBN #

0931837669

Eliot K Broadbent from Beaverton, OR, age ~69 Get Report