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Eli S Chiprout

from Port Townsend, WA
Age ~65
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Also known as:
Eli C Chiproot
Related to:
Celange M Murphy, 48Talia Chiprout, 30Lia A Roth, 58Jeremy Roth, 50Anthony T Roth, 51Carol L Arnett, 64Julie A Harness, 52
Connected to:
Michael C Chipser, 41Rhonda M Chipy, 51Frank Chiquete, 49Rosa M Chiquete, 62Julio C Chiqui, 49Luis Chiqui, 55Camilo ChiquilloJoanna A Chiquillo, 38Monica P Chiquillo, 56Raquel P Chiquillo, 53

Eli Chiprout Phones & Addresses

  • Port Townsend, WA
  • 14908 NW Twinflower Dr, Portland, OR 97229 (503) 764-8590
  • Tempe, AZ
  • Austin, TX
  • Ossining, NY
  • Maricopa, AZ
  • Mount Kisco, NY
  • 14908 NW Twinflower Dr, Portland, OR 97229

Work

Position: Researcher

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Carleton University 1990 to 1994 Specialities: Electronics Engineering, Philosophy

Skills

Eda • Microprocessors • Cad • Simulations • Semiconductor Process • Research • Semiconductors • Interconnects • Algorithms • Application Specific Integrated Circuits • Electronics Packaging • Validation • Data Mining • Algorithm Development • Statistical Data Analysis • Debugging • C++ • System on A Chip • Integrated Circuits • Testing • C • Very Large Scale Integration

Languages

English • French • Hebrew

Industries

Research

Resumes

Resumes

Eli Chiprout Photo 1

Researcher

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Location:
Port Townsend, WA
Industry:
Research
Work:

Researcher
Intel Corporation
Principal Engineer
Self Employed - Engineering Consulting
Principal Engineer
Intel Corporation 2000 - 2016
Principal Research Engineer
Ibm Nov 1994 - Dec 2000
Research Staff Member
Education:
Carleton University 1990 - 1994
Doctorates, Doctor of Philosophy, Electronics Engineering, Philosophy Mcgill University 1985 - 1988
Bachelor of Engineering, Bachelors, Electronics Engineering, Engineering
Skills:
Eda
Microprocessors
Cad
Simulations
Semiconductor Process
Research
Semiconductors
Interconnects
Algorithms
Application Specific Integrated Circuits
Electronics Packaging
Validation
Data Mining
Algorithm Development
Statistical Data Analysis
Debugging
C++
System on A Chip
Integrated Circuits
Testing
C
Very Large Scale Integration
Languages:
English
French
Hebrew

Publications

Us Patents

Operating System Support For In-Server Caching Of Documents

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US Patent:
6442654, Aug 27, 2002
Filed:
Dec 10, 1999
Appl. No.:
09/458406
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711141, 711130, 711144, 711160
Abstract:
A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.

System For Dynamically Adjusting Image Quality For Interactive Graphics Applications

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US Patent:
6473085, Oct 29, 2002
Filed:
Dec 17, 1999
Appl. No.:
09/465295
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1516
US Classification:
345502, 345418, 709105
Abstract:
A method and system for optimizing image quality while operating an interactive graphics application within a data processing system. First, the image rendering speed for each of the rendering modes available within the interactive graphics application are assessed. Upon initial operation of the interactive graphics system, a default rendering mode is activated. During operation of the interactive graphics application, the processing load imposed on the data processing system is monitored and utilized as a user activity metric. The active rendering mode is updated in accordance with the user activity metric, such that the speed of the selected rendering mode varies inversely with the current processing load.

Efficient Identification Of Candidate Pages And Dynamic Response In A Numa Computer

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US Patent:
6499028, Dec 24, 2002
Filed:
Mar 31, 1999
Appl. No.:
09/282625
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
David Brian Glasco - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1700
US Classification:
707 4, 714 47, 709249
Abstract:
A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks. In the preferred embodiment, the plurality of block counters are implemented with a random access memory device.

Memory Transaction Monitoring System And User Interface

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US Patent:
6601149, Jul 29, 2003
Filed:
Dec 14, 1999
Appl. No.:
09/460831
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711154
Abstract:
A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information. The data processing system may operate under a first operating system such as a Unix based system while the monitoring system operates under a second operating system such as a Windows operating system.

Method, Apparatus And System For Inductance Modeling In An Electrical Configuration

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US Patent:
7325208, Jan 29, 2008
Filed:
Sep 28, 2004
Appl. No.:
10/950676
Inventors:
Sourav Chakravarty - Hillsboro OR, US
Yaakov Ben-Noon - Herzlia, IL
Eli Chiprout - Tempe AZ, US
Mohiuddin Mazumder - San Jose CA, US
Dmitry Messerman - Haifa, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 4
Abstract:
Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include determining a plurality of two-dimensional mutual inductance values corresponding to a designated victim within a geometrical event and a plurality of designated attackers, respectively. Other embodiments are described and claimed.

Performance Monitoring In A Numa Computer

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US Patent:
6349394, Feb 19, 2002
Filed:
Mar 31, 1999
Appl. No.:
09/282626
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
David Brian Glasco - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1100
US Classification:
714 47, 709249
Abstract:
A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the systems physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.

Isbn (Books And Publications)

Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis

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Author

Eli Chiprout

ISBN #

0792394135

Control profile
Eli S Chiprout from Port Townsend, WA, age ~65 Get Report