Eiji Kasahara

7395411, Jul 1, 2008

Mar 14, 2005

11/079565

Eiji Kasahara - Austin TX, US

Sony Computer Entertainment Inc. - Tokyo

G06F 9/312
G06F 9/315

712200

Methods and apparatus provide for performing pre-execution processes to prepare instructions of an instruction set for further processing; executing the instructions in a pipeline of execution stages using digital logic for processing data in accordance with the instructions within one clock cycle per stage; latching the data each clock cycle for delivery to a next execution stage using one or more of a plurality of latch point circuits; and controlling each of the latch point circuits to operate as a buffer or as a latch.

7790987, Sep 7, 2010

Apr 27, 2005

11/116066

Eiji Kasahara - Austin TX, US
Hiroshi Katoh - Austin TX, US

Sony Computer Entertainment Inc. - Tokyo

H05K 1/16

174260

Methods and apparatus provide for connecting an integrated circuit having a ball grid array to a printed circuit board having a matrix of contact pads for electrical connection to the ball grid array.

8176481, May 8, 2012

Sep 20, 2005

11/231131

Eiji Kasahara - Austin TX, US

Sony Computer Entertainment Inc.

G06F 9/44

717168, 712200, 717169, 717170

Methods and apparatus for enabling execution of software programs permit: obtaining identification information that is indicative of a version of a software program; determining whether processing capabilities of a processor on which the software program is to be executed are incompatible with proper execution of the version of the software program; and at least partially modifying the version of the software program to obtain a more suitable version of the software program that will execute properly on the processor.

20060107122, May 18, 2006

Sep 20, 2005

11/230748

Eiji Kasahara - Austin TX, US

Sony Computer Entertainment Inc. - Tokyo

G06F 11/00

714038000

Methods and apparatus for adjusting processing capabilities permit obtaining identification information that is indicative of a version of a software program stored in the storage medium; determining whether processing capabilities of one or more processors on which the software program is to be executed should be adjusted in accordance with the version of the software program; and adjusting the processing capabilities of the one or more processors when the determination is in the affirmative.

20060206732, Sep 14, 2006

Mar 14, 2005

11/079566

Eiji Kasahara - Austin TX, US

G06F 1/26

713300000

Methods and apparatus provide for a processor fabricated using a fabrication process of X nano-meters, which is an advanced process over a Y nano-meter process; and increasing a depth of a dependency check circuit of the processor in response to the advanced fabrication process to improve processing power, where the dependency check circuit is operable to determine whether operands of incoming instructions to a pipeline are dependent on operands of any other instructions being executed in the pipeline

6367032, Apr 2, 2002

Jul 14, 2000

09/615659

Eiji Kasahara - Sunnyvale CA

Sony Corporation of Japan - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

G60F 1100

714 25, 714 30

Method and system for debugging a microprocessor core. In one embodiment, the method comprises the step of receiving as input a test program and test data for testing the microprocessor core. The method also comprises the step of storing multiple instructions of the test program into a first register of a debugging module in the microprocessor core. The method further comprises the step of storing a set of data into a second register of the debugging module, wherein the set of data is a subset of the test data. The method also comprises the step of executing those multiple instructions with the set of data. Importantly, those multiple instructions remain in the first register throughout the testing process such that those instructions need only be stored once for all of the test data, even though the test data is processed in separate sets of data. In one embodiment, the present invention includes the above and wherein the debugging module is based on a version of the IEEE 1149. 1 standard.