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Edward John Spall

from Manassas, VA
Age ~84
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Also known as:
Edward J Spall, Edward D Spall, Joann Elaine Spall, Edward John Spall Revocabl, Joann E Spall
Phone and address:
9613 Gladstone St, Manassas, VA 20110
(703) 369-0133
Related to:
Vincent Anthony Vena, 63Richard SpallShirley VenaJohn Vena, 88
Connected to:
Mark S Spall, 67Melissa C Spall, 56Peter N Spall, 38Sally A Spall, 89Andrea E Spalla, 78Anthony L Spalla, 45David C Spalla, 39Laura J Spalla, 60Marilyn K Spalla, 64Mildred L Spalla, 105

Edward Spall Phones & Addresses

  • 9613 Gladstone St, Manassas, VA 20110 (703) 369-0133
  • Auburn Hills, MI
  • Chauvin, LA

Industries

Electrical/Electronic Manufacturing

Public records

Vehicle Records

Edward Spall

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Address:
9613 Gladstone St, Manassas, VA 20110
VIN:
KMHGC4DE1AU089473
Make:
HYUNDAI
Model:
GENESIS
Year:
2010

Resumes

Resumes

Edward Spall Photo 1

President And Ceo At Ovonyx Technologies Inc.

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Location:
Greater Detroit Area
Industry:
Electrical/Electronic Manufacturing

Business Records

Name / Title
Company / Classification
Phones & Addresses
Edward Spall
President
Spall Inc
Painting/Paper Hanging Contractor
10407 Spraggins Ct, Manassas, VA 20110
(703) 330-9980
Edward Spall
President
OVONYX TECHNOLOGIES, INC
2956 Waterview Dr, Rochester, MI 48309

Publications

Us Patents

Memory Device

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US Patent:
6567296, May 20, 2003
Filed:
Oct 24, 2001
Appl. No.:
10/041684
Inventors:
Giulio Casagrande - Vignate, IT
Tyler Lowrey - San Jose CA
Roberto Bez - Milan, IT
Guy Wicker - Southfield MI
Edward Spall - Manassas VA
Stephen Hudgens - Santa Clara CA
Wolodymyr Czubatyj - Warren MI
Assignee:
STMicroelectronics S.r.l. - Agrate Brianza
Ovonyx, Inc. - Troy MI
International Classification:
G11C 1706
US Classification:
365105, 365175
Abstract:
A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

Phase Change Memory Latch

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US Patent:
7471554, Dec 30, 2008
Filed:
Jan 27, 2006
Appl. No.:
11/341983
Inventors:
Edward J. Spall - Manassas VA, US
Tyler Lowrey - West Augusta VA, US
Assignee:
Ovonyx, Inc. - Rochester Hills MI
International Classification:
G11C 11/00
US Classification:
365163, 365154, 36518916
Abstract:
A non-volatile memory latch may be formed with a phase change memory layer. Such a latch may be faster and more easily integrated into main stream semiconductor processes than conventional latches that use non-volatile memory elements such as flash memory.

Die Customization Using Programmable Resistance Memory Elements

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US Patent:
7663907, Feb 16, 2010
Filed:
Sep 19, 2005
Appl. No.:
11/229955
Inventors:
Tyler Lowrey - West Augusta VA, US
Guy C. Wicker - Southfield MI, US
Edward J. Spall - Manassas VA, US
Assignee:
Ovonyx, Inc. - Rochester Hills MI
International Classification:
G11C 11/00
US Classification:
365148, 365171, 365158
Abstract:
A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.

Breakdown Layer Via Lateral Diffusion

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US Patent:
8350661, Jan 8, 2013
Filed:
May 26, 2009
Appl. No.:
12/471937
Inventors:
Wolodymyr Czubatyj - Warren MI, US
Tyler Lowrey - Rochester Hills MI, US
Edward J. Spall - Manassas VA, US
Assignee:
Ovonyx, Inc. - Sterling Heights MI
International Classification:
H01C 7/13
US Classification:
338 22R
Abstract:
An electronic device including a breakdown layer having variable thickness. The device includes a variable resistance material positioned between two electrodes. A breakdown layer is interposed between the variable resistance material and one of the electrodes. The breakdown layer has a non-uniform thickness, which serves to bias the breakdown event toward the thinner portions of the breakdown layer. As a result, the placement, size, and number of ruptures in the breakdown layer are more consistent over a series or array of devices. The variable resistance material may be a phase-change material. The variable-thickness breakdown layer may be formed through a diffusion process by introducing a gas containing a resistivity-enhancing species to the environment of segmented variable resistance devices during fabrication. The resistivity-enhancing element penetrates the outer perimeter of the variable resistance material and diffuses toward the interior of the device. The resistivity-enhancing species increases the resistance of the interface between the variable resistance material and the electrode by interacting with the variable resistance material and/or electrode to form a resistive interfacial material.

Die Customization Using Programmable Resistance Memory Elements

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US Patent:
20100201697, Aug 12, 2010
Filed:
Feb 15, 2010
Appl. No.:
12/705639
Inventors:
Tyler Lowrey - West Augusta VA, US
Guy C. Wicker - Southfield MI, US
Edward J. Spall - Manassas VA, US
International Classification:
G09G 5/39
US Classification:
345531
Abstract:
A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.

Multichip Module With Integrated Test Circuitry Disposed Within Interposer Substrate

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US Patent:
55175155, May 14, 1996
Filed:
Aug 17, 1994
Appl. No.:
8/292120
Inventors:
Edward J. Spall - Manassas VA
Thomas M. Storey - Manassas VA
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
G06F 1100
US Classification:
371 225
Abstract:
A multichip module (MCM) and associated fabrication technique are presented wherein a test circuit is disposed within the interposer substrate of the MCM to facilitate testing of the module's integrated circuit chips and testing of the interconnect wiring between integrated circuit chips. The test circuitry, disposed within the interposer substrate comprises semiconductor logic circuitry that electrically connects to the integrated circuit chips of the module. In the various multiplexer latch and shift register latch embodiments disclosed, active test circuitry within the interposer substrate is minimized and is essentially transparent to the integrated circuit chip designs incorporated in the MCM.
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Edward John Spall from Manassas, VA, age ~84 Get Report