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Eduard A Cartier

from New York, NY
Age ~73
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Also known as:
Edward A Cartier
Phone and address:
101 W 85Th St APT 6-6, New York, NY 10024
(631) 598-1194
Related to:
Savannah M Cartier, 23
Connected to:
Alison Cartier, 52Arienne L Cartier, 49Barbara E Cartier, 76Dolores Cartier, 103Edward Cartier, 74Irene T Cartier, 93Jasmine L Cartier, 58Jeanne M Cartier, 63Laurie E Cartier, 60Mark E Cartier, 65

Eduard Cartier Phones & Addresses

  • 101 W 85Th St APT 6-6, New York, NY 10024 (631) 598-1194
  • 101 85Th St, New York, NY 10024
  • 101 W 85Th St APT 6-JUN, New York, NY 10024

Work

Company: Ibm t.j. watson research center, new york, usa Sep 1988 Position: Research staff member

Education

Degree: Doctor of Philosophy (PhD) School / High School: Eidgenössische Technische Hochschule Zürich 1978 to 1982 Specialities: Phsics

Skills

Characterization • Physics • Cmos • Semiconductors • Nanotechnology • Thin Films • Failure Analysis • Materials Science • Simulations • Design of Experiments • Process Integration • Vlsi • Research and Development • Microelectronics • Silicon • R&D • Reliability • Ic • Electronics • Semiconductor Industry • Electrical Engineering • Atomic Layer Deposition • Asic

Languages

German • French

Industries

Semiconductors

Resumes

Resumes

Eduard Cartier Photo 1

Research Staff Member

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Location:
New York, NY
Industry:
Semiconductors
Work:
IBM T.J. Watson Research Center, New York, USA since Sep 1988
Research Staff Member
Education:
Eidgenössische Technische Hochschule Zürich 1978 - 1982
Doctor of Philosophy (PhD), Phsics
Skills:
Characterization
Physics
Cmos
Semiconductors
Nanotechnology
Thin Films
Failure Analysis
Materials Science
Simulations
Design of Experiments
Process Integration
Vlsi
Research and Development
Microelectronics
Silicon
R&D
Reliability
Ic
Electronics
Semiconductor Industry
Electrical Engineering
Atomic Layer Deposition
Asic
Languages:
German
French

Publications

Us Patents

Reactive Sputtering Method For Forming Metal-Silicon Layer

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US Patent:
6413386, Jul 2, 2002
Filed:
Jul 19, 2000
Appl. No.:
09/619512
Inventors:
Alessandro Cesare Callegari - Yorktown Heights NY
Eduard Albert Cartier - New York NY
Michael Abramovich Gribelyuk - Poughquag NY
Theodore Harold Zabel - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C23C 1434
US Classification:
20419223, 136257, 438142, 438381, 438800
Abstract:
Within a method for forming a metal-silicon layer there is first provided a reactor chamber. There is then positioned within the reactor chamber a substrate spaced from a metal source target. There is also provided within the reactor chamber a minimum of a sputter material and a reactive silicon material. There is then sputtered the metal source target positioned within the reactor chamber with the sputter material provided within the reactor chamber in the presence of the reactive silicon material provided within the reactor chamber to form a metal-silicon layer over the substrate. The method is particularly useful for forming metal silicate layers, metal silicon nitride layers and metal silicon oxynitride layers within microelectronic fabrications. An alternative method employs: (1) a silicon source target rather than a metal source target; and (2) a reactive metal material rather than a reactive silicon material.

Interfacial Oxidation Process For High-K Gate Dielectric Process Integration

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US Patent:
6444592, Sep 3, 2002
Filed:
Jun 20, 2000
Appl. No.:
09/597765
Inventors:
Arne W. Ballantine - Round Lake NY
Douglas A. Buchanan - Cortlandt Manor NY
Eduard A. Cartier - New York NY
Kevin K. Chan - Staten Island NY
Matthew W. Copel - Yorktown Heights NY
Christopher P. DEmic - Ossining NY
Evgeni P. Gousev - Mahopac NY
Fenton Read McFeely - Ossining NY
Joseph S. Newbury - Tarrytown NY
Patrick R. Varekamp - Croton-on-Hudson NY
Theodore H. Zabel - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21469
US Classification:
438770
Abstract:
A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 ; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Deuterium Reservoirs And Ingress Paths

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US Patent:
6521977, Feb 18, 2003
Filed:
Jan 21, 2000
Appl. No.:
09/489277
Inventors:
Jay Burnham - E. Fairfield VT
Eduard A. Cartier - New York NY
Thomas G. Ference - Essex Junction VT
Steven W. Mittl - Essex VT
Anthony K. Stamper - Williston VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2358
US Classification:
257649, 257640, 257618, 257622, 257629, 257774, 257761, 438 98, 438162, 438240, 438407, 438683, 438686, 438624, 438625, 438589, 438618, 438622, 438627, 438629, 438637, 438648, 438650, 438675
Abstract:
Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

Method For Forming Dielectric Stack Without Interfacial Layer

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US Patent:
6528374, Mar 4, 2003
Filed:
Feb 5, 2001
Appl. No.:
09/777094
Inventors:
Eduard A. Cartier - New York NY
Matthew W. Copel - Yorktown Heights NY
Supratik Guha - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 20336
US Classification:
438299, 438204, 438287, 438404, 438624
Abstract:
A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800Â C. and about 1000Â C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Engineered High Dielectric Constant Oxide And Oxynitride Heterostructure Gate Dielectrics By An Atomic Beam Deposition Technique

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US Patent:
6541079, Apr 1, 2003
Filed:
Oct 25, 1999
Appl. No.:
09/426656
Inventors:
Eduard A. Cartier - New York City NY
Supratik Guha - Croton-on-Hudson NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C23C 1408
US Classification:
427527, 427529, 427530, 42725529, 427255394
Abstract:
A method of forming a layer of oxide or oxynitride upon a substrate including first placing a substrate having an upper surface and a lower surface in a high vacuum chamber and then exposing the upper surface to a beam of atoms or molecules, or both, of oxygen or nitrogen or a combination of same at a temperature sufficient to form a reacted layer on the upper surface of said substrate wherein said layer has a chemical composition different from the chemical composition of said substrate. The reacted upper layer is then exposed simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or metal molecules selected from the group consisting of Al, Si, Zr, La, Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer in said layer. Another option is to expose the upper surface of the substrate simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or meal molecules selected from the group consisting of Al, Si, Zr, La Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer on said reacted layer.

Method For Non-Contact Stress Evaluation Of Wafer Gate Dielectric Reliability

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US Patent:
6602772, Aug 5, 2003
Filed:
Dec 4, 2001
Appl. No.:
10/006969
Inventors:
Wagdi W. Abadeer - Jericho VT
Eduard A. Cartier - New York NY
James H. Stathis - Poughquag NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 213205
US Classification:
438585, 438710, 438779, 257410, 118723 ER, 31511121, 31511181
Abstract:
An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric. The method may be conducted on a remote-plasma hydrogen exposure apparatus comprising, in series, a source of a mixture of molecular and atomic hydrogen gas; a particle remover adapted to remove energetic, charged particles; a light sink; a hydrogen recombination device; and a wafer exposure chamber.

Mos Device Having A Passivated Semiconductor-Dielectric Interface

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US Patent:
6603181, Aug 5, 2003
Filed:
Jan 16, 2001
Appl. No.:
09/760621
Inventors:
Paul M. Solomon - Yorktown Heights NY
Douglas A. Buchanan - Cortland Manor NY
Eduard A. Cartier - New York NY
Kathryn W. Guarini - Yorktown Heights NY
Fenton R. McFeely - New York NY
Huiling Shang - Bethlehem PA
John J. Yourkas - Stamford CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2976
US Classification:
257412, 438910
Abstract:
A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

Silicate Gate Dielectric

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US Patent:
6753556, Jun 22, 2004
Filed:
Oct 6, 1999
Appl. No.:
09/413462
Inventors:
Eduard Albert Cartier - New York NY
Matthew Warren Copel - Yorktown Heights NY
Frances Mary Ross - Stamford CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257213, 257381, 257388, 438142
Abstract:
A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing gas is provided. Semiconductor structures comprising the metal silicate formed over a SiO layer are also disclosed herein.
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Eduard A Cartier from New York, NY, age ~73 Get Report