Inventors:
Dwight D. Hill - Holmdel NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G11C 1100
Abstract:
A field programmable array of application circuitry (C1, C2,. . . ) is programmed (or reprogrammed) by first applying application circuitry power supply (AV. sub. dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is typically one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The source-drain path of each pass transistor is connected between a separate pair of application circuitry interconnection points (A1, A2), whereby the on/off condition of this pass transistor determines whether or not these two points are going to be connected after the programming (or reprogramming) is terminated. While the data signal (D0/D1) is thus being applied to the SRAM, and while the power supply (PV. sub. DD) for the SRAM is being maintained at an intermediate level (3v) below the level of the application circuitry power supply voltage (AV. sub.