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Dwayne M Burek

from Truckee, CA
Age ~63
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Also known as:
Dwayne M Urek
Connected to:
Alexandria Burek, 42Annastasia K Burek, 32Danielle M Burek, 37Denis E Burek, 69Diana M Burek, 77Douglas J Burek, 53Georgia A Burek, 63Glenn J Burek, 66Ismir Burek, 46Judith A Burek, 76

Dwayne Burek Phones & Addresses

  • Truckee, CA
  • 5649 Le Fevre Dr, San Jose, CA 95118 (408) 265-5595
  • Santa Clara, CA
  • Novato, CA
  • 5649 Le Fevre Dr, San Jose, CA 95118 (925) 984-3785

Work

Company: Broadcom Aug 2008 Position: Dft engineer

Education

Degree: Master of Science in Electrical Engineering School / High School: University of Manitoba 1987 to 1990

Skills

Dft • Eda • Atpg • Semiconductors • Integrated Circuit Design • Asic • Bist • Soc • Testing • Design For Manufacturing • Product Engineering • Product Marketing • Boundary Scan • Product Management • Physical Verification

Industries

Semiconductors

Resumes

Resumes

Dwayne Burek Photo 1

Dft Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Broadcom since Aug 2008
DFT Engineer
Magma Design Automation Dec 2007 - Jun 2008
Product Director (DFM), Physical Verification Business Unit
Magma Jun 2005 - Dec 2007
Product Director, Design Implementation Business Unit
Magma Design Automation Jul 2003 - Jun 2005
Product Engineer
LogicVision, Inc. 1994 - 2003
Product Marketing
Education:
University of Manitoba 1987 - 1990
Master of Science in Electrical Engineering
Skills:
Dft
Eda
Atpg
Semiconductors
Integrated Circuit Design
Asic
Bist
Soc
Testing
Design For Manufacturing
Product Engineering
Product Marketing
Boundary Scan
Product Management
Physical Verification

Publications

Us Patents

Method And Program Product For Modeling Circuits With Latch Based Design

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US Patent:
6457161, Sep 24, 2002
Filed:
Mar 27, 2001
Appl. No.:
09/817298
Inventors:
Benoit Nadeau-Dostie - Aylmer, Quebec, CA
Fadi Maamari - San Jose CA, 95125
Dwayne Burek - San Jose CA, 95118
International Classification:
G06F 1750
US Classification:
716 6, 716 3
Abstract:
A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.

Method And Apparatus For Testing High Performance Circuits

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US Patent:
6510534, Jan 21, 2003
Filed:
Jun 29, 2000
Appl. No.:
09/607128
Inventors:
Benoit Nadeau-Dostie - Aylmer, CA
Fadi Maamari - San Jose CA
Dwayne Burek - San Jose CA
Jean-Francois Cote - Chelsea, CA
Assignee:
LogicVision, Inc. - San Jose CA
International Classification:
G01R 3128
US Classification:
714724, 714726, 714729, 714731
Abstract:
A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks.

Hierarchical Design And Test Method And System, Program Product Embodying The Method And Integrated Circuit Produced Thereby

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US Patent:
6615392, Sep 2, 2003
Filed:
Jul 27, 2000
Appl. No.:
09/626877
Inventors:
Benoit Nadeau-Dostie - Aylmer, CA
Dwayne Burek - San Jose CA
Jean-Francois Cote - Chelsea, CA
Sonny Ngai San Shum - San Jose CA
Pierre Girouard - San Jose CA
Pierre Gauther - Aylmer, CA
Sai Kennedy Vedantam - Saratoga CA
Luc Romain - Aylmer, CA
Charles Bernard - Hollister CA
Assignee:
Logicvision, Inc. - San Jose CA
International Classification:
G06F 945
US Classification:
716 5, 716 4, 716 18
Abstract:
A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.

Method And Program Product For Designing Hierarchical Circuit For Quiescent Current Testing

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US Patent:
6862717, Mar 1, 2005
Filed:
Dec 17, 2001
Appl. No.:
10/015751
Inventors:
Benoit Nadeau-Dostie - Aylmer, CA
Dwayne Burek - San Jose CA, US
Assignee:
LogicVision, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 4, 716 2, 716 7, 716 18
Abstract:
A method of designing a circuit having at least one hierarchical block which requires block specific test patterns to facilitate quiescent current testing of the circuit, comprises, for each block, configuring the block and any embedded blocks located one level down in design hierarchy in quiescent current test mode in which input and output peripheral memory elements are configured in internal test mode and in external test mode, respectively; generating quiescent current test patterns which do not result in elevated quiescent current levels and which include a bit for all memory elements in the block and for any peripheral memory elements in any embedded blocks located one level down in design hierarchy; and, if the block contains embedded blocks, synchronizing the test pattern with a corresponding test pattern generated for embedded blocks so that test patterns loaded in scan chains in the block are consistent with test patterns loaded in scan chains in said embedded blocks.

Asynchronous Control Of Memory Self Test

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US Patent:
7203873, Apr 10, 2007
Filed:
Jun 4, 2004
Appl. No.:
10/861247
Inventors:
R. Dean Adams - St. George VT, US
Robert Abbott - Ottawa, CA
Xiaoliang Bai - La Jolla CA, US
Dwayne M. Burek - San Jose CA, US
Assignee:
Magma Design Automation, Inc. - Santa Clara CA
International Classification:
G11C 29/00
US Classification:
714718, 714733, 714 31
Abstract:
A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.
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Dwayne M Burek from Truckee, CA, age ~63 Get Report