Dustin K Slisher

8234001, Jul 31, 2012

Sep 28, 2009

12/568083

James Rice - Hopewell Junction NY, US
Dustin K. Slisher - Hopewell Junction NY, US
Yunsheng Song - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G06F 19/00

700110, 700109, 702 84, 702185

A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.

8298904, Oct 30, 2012

Jan 18, 2011

13/008465

Joseph M. Lukaitis - Pleasant Valley NY, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
Dustin K. Slisher - Wappingers Falls NY, US
Timothy D. Sullivan - Underhill VT, US

International Business Machines Corporation - Armonk NY

H01L 21/20

438384, 438385, 257E21004

A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

8486796, Jul 16, 2013

Nov 19, 2010

12/950635

David L. Harmon - Essex VT, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Robert R. Robison - Colchester VT, US
Dustin K. Slisher - Wappingers Falls NY, US
Jeffrey H. Sloan - Chittenden VT, US
Timothy D. Sullivan - Franklin Lakes NJ, US
Kimball M. Watson - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

H01L 21/8222
H01L 23/62

438330, 438382, 257359, 257380, 257E27113, 257E27114

A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.

8541864, Sep 24, 2013

Aug 17, 2012

13/588218

Joseph M. Lukaitis - Pleasant Valley NY, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
Dustin K. Slisher - Wappingers Falls NY, US
Timothy D. Sullivan - Underhill VT, US

International Business Machines Corporation - Armonk NY

H01L 29/02

257506, 257E2902

A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

8610217, Dec 17, 2013

Dec 14, 2010

12/967114

Mahender Kumar - Fishkill NY, US
Junjun Li - Williston VT, US
Dustin K. Slisher - Wappingers Falls NY, US

International Business Machines Corporation - Armonk NY

H01L 23/62

257360, 257E27035

Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e. g. , without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

20060234401, Oct 19, 2006

Apr 19, 2005

10/907870

Dustin Slisher - Wappingers Falls NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 21/66

438014000

A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the kerfs that surround the integrated circuit chips. Leakage current between the gate and the source-drain region is measured at FETs in each kerf. Based on the measurement, a leakage current map is created and compared to a standard map. In accordance with this comparison and to the distribution of patterns of leakage currents, it is determined whether or not the wafer is defective. This determination is performed in the kerfs after formation of the gate and source-drain regions, and prior to the wafer being completed. By detecting defective wafers at an early stage, considerable manufacturing resources are saved.

20120181663, Jul 19, 2012

Jan 18, 2011

13/008459

Joseph M. LUKAITIS - Pleasant Valley NY, US
Jed H. RANKIN - Richmond VT, US
Robert R. ROBISON - Colchester VT, US
Dustin K. SLISHER - Wappingers Falls NY, US
Timothy D. SULLIVAN - Underhill VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/8605
H01L 21/02

257536, 438384, 257E21004, 257E29326

A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.

20120187529, Jul 26, 2012

Jan 25, 2011

13/013055

Edward P. Maciejewski - Hopewell Junction NY, US
Dustin Kenneth Slisher - Hopewell Junction NY, US
Stefan Zollner - Las Cruces NM, US

International Business Machines Corporation - Armonk NY

H01L 23/525
H01L 21/02

257529, 438381, 257E23149, 257E21003

An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.