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Duncan Gurley Phones & Addresses

  • 1159 Blewett Ave, San Jose, CA 95125 (408) 768-8363
  • Campbell, CA
  • 1159 Blewett Ave, San Jose, CA 95125

Publications

Us Patents

Wafer Test Head Architecture And Method Of Use

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US Patent:
7378860, May 27, 2008
Filed:
Sep 22, 2006
Appl. No.:
11/525731
Inventors:
Erik Volkerink - San Jose CA, US
Duncan Gurley - San Jose CA, US
Ajay Khoche - San Jose CA, US
Assignee:
Verigy (Singapore) Pte. Ltd. - Singapore
International Classification:
G01R 31/02
US Classification:
324754
Abstract:
A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.

System And Method For Electronic Testing Of Multiple Memory Devices

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US Patent:
7707468, Apr 27, 2010
Filed:
Mar 22, 2007
Appl. No.:
11/726542
Inventors:
Erik Volkerink - Palo Alto CA, US
Duncan Gurley - San Jose CA, US
Assignee:
Verigy (Singapore) Pte. Ltd - Singapore
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.

Apparatus And Method For Using Mems Filters To Test Electronic Circuits

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US Patent:
20060174177, Aug 3, 2006
Filed:
Feb 2, 2005
Appl. No.:
11/049076
Inventors:
Michael Weinstein - Los Altos CA, US
Duncan Gurley - San Jose CA, US
International Classification:
G01R 31/28
G06F 11/00
US Classification:
714742000
Abstract:
A mixed-signal integrated circuit testing device includes test electronics for generating a test signal for input to a device under test and receiving a response signal from the device under test, and an interface connected between the test electronics and the device under test. The interface includes at least one Micro Electro-Mechanical Systems (MEMS) filter for filtering an analog signal associated with one of the test signal and the response signal.

Data Converter With Integrated Mems Resonator Clock

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US Patent:
20070052565, Mar 8, 2007
Filed:
Sep 6, 2005
Appl. No.:
11/220280
Inventors:
Michael Weinstein - Los Altos CA, US
Duncan Gurley - San Jose CA, US
International Classification:
H03M 1/66
US Classification:
341144000
Abstract:
An improved clocked data converter with a vibrating microelectromechanical systems (MEMS) resonator. The MEMS resonator is used as part of the clock circuitry of an analog to digital converter or a digital to analog converter. The MEMS resonator may be used as the frequency determining element of an on-chip oscillator, or as a bandpass filter used to clean up an external clock signal.

Wafer Boat For Semiconductor Testing

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US Patent:
20090053837, Feb 26, 2009
Filed:
Aug 24, 2007
Appl. No.:
11/895590
Inventors:
Ajay Khoche - San Jose CA, US
Duncan Gurley - San Jose CA, US
Assignee:
Verigy (Singapore) Pte. Ltd. - Fort Collins CO
International Classification:
H01L 21/66
G01R 31/26
US Classification:
438 14, 324765, 257E21521
Abstract:
In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.

Methods, Apparatus, And Systems For Contacting Semiconductor Dies That Are Electrically Coupled To Test Access Interface Positioned In Scribe Lines Of A Wafer

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US Patent:
20140002122, Jan 2, 2014
Filed:
Jun 30, 2011
Appl. No.:
14/005311
Inventors:
Larry John Dibattista - Cupertino CA, US
Duncan Packard Gurley - Cupertino CA, US
Assignee:
ADVANTEST (SINGAPORE) PTE. LTD. - Singapore
International Classification:
G01R 1/04
G06F 17/50
H01L 21/66
US Classification:
32475024, 257 48, 716119, 32475603
Abstract:
A semiconductor device includes a first wafer having i) a plurality of semiconductor dies, ii) a plurality of scribe lines adjacent one or more of the semiconductor dies, iii) a test access interface positioned in one or more of the scribe lines, wherein the test access interface has a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the through-substrate conductors and at least one of the semiconductor dies. Methods, apparatus and systems for testing this and other types of semiconductor devices are also disclosed.

System, Methods And Apparatus Using Virtual Appliances In A Semiconductor Test Environment

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US Patent:
20150370248, Dec 24, 2015
Filed:
Aug 31, 2015
Appl. No.:
14/840860
Inventors:
Klaus-Dieter Hilliges - Shanghai, CN
Jia-Wei Lin - Shanghai, CN
Duncan Gurley - Cupertino CA, US
Jim-my Jin - Shanghai, CN
Eric Volkerink - Cupertino CA, US
Assignee:
ADVANTEST CORPORATION - TOKYO
International Classification:
G05B 19/418
Abstract:
In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.

System, Methods And Apparatus Using Virtual Appliances In A Semiconductor Test Environment

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US Patent:
20140189430, Jul 3, 2014
Filed:
Sep 7, 2010
Appl. No.:
13/821559
Inventors:
Klaus-Dieter Hilliges - Shanghai, CN
Jia-Wei Lin - Shanghai, CN
Duncan Gurley - Cupertino CA, US
Jimmy Xiaomin Jin - Shanghai, CN
Erik H. Volkerink - Cupertino CA, US
Assignee:
VERIGY (SINGAPORE) PTE. LTD. - Singapore
International Classification:
G06F 11/07
G06F 9/455
G06F 11/22
US Classification:
714 27
Abstract:
In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
Duncan P Gurley from San Jose, CA, age ~66 Get Report