US Patent:
20230114164, Apr 13, 2023
Inventors:
- Santa Clara CA, US
Aravindh Anantaraman - Folsom CA, US
Lakshminarayana Pappu - Folsom CA, US
Dongsheng Bi - Fremont CA, US
Guadalupe J. Garcia - Chandler AZ, US
Altug Koker - El Dorado Hills CA, US
Joydeep Ray - Folsom CA, US
Rahul Joshi - Pune, IN
Shrikul Atulkumar Joshi - Rajkot, IN
Mahak Gupta - Bengaluru, IN
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/0871
G06F 12/0891
G06F 13/16
G06F 13/28
G06F 15/78
Abstract:
In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.