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Donald L Wheater

from Hinesburg, VT
Age ~64
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Also known as:
Don Wheater
Phone and address:
564 Buck Hill Rd, Mechanicsburg, VT 05461
(802) 482-4265
Related to:
Kevin D Rocheleau, 69Nicole Rocheleau, 31
Connected to:
Charles C Wheater, 82Tonia E Wheatfall, 56Barbara A Wheatfill, 81Frank C Wheatlake, 77Tiffany C Wheatland, 42Alex F Wheatley, 77Alexandra Wheatley, 32Allan Wheatley, 91Alyse G Wheatley, 49Annie B Wheatley, 69

Donald Wheater Phones & Addresses

  • 564 Buck Hill Rd, Hinesburg, VT 05461 (802) 482-4265
  • Putnam Station, NY
  • Essex Junction, VT
  • Ticonderoga, NY

Interests

consulting offers, new ventures, experti...

Industries

Semiconductors

Resumes

Resumes

Donald Wheater Photo 1

Donald Wheater

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Location:
Burlington, Vermont Area
Industry:
Semiconductors
Experience:
IBM (Public Company; Semiconductors industry): Senior Technical Staff Member,  (1974-2007) International Business Machines (Semiconductors industry): Senior Technical Staff Member,  (1974-2007) 

Publications

Us Patents

Single Pin Performance Screen Ring Oscillator With Frequency Division

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US Patent:
6426641, Jul 30, 2002
Filed:
Oct 21, 1998
Appl. No.:
09/177139
Inventors:
Steven P. Koch - Underhill VT
Donald L. Wheater - Hinesburg VT
Larry Wissel - Williston VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
324765, 3241581, 324763
Abstract:
An oscillator circuit on a chip with a single I/O node whose output generally corresponds to a performance level of the IC chip. The single I/O node provides an easy access and testing point for evaluating chip performance. The I/O node is used for coupling to the oscillator circuit, and for activating and monitoring its oscillating output signal. The single I/O node may be accessed at the wafer level, after packaging, or in the field.

Structures For Wafer Level Test And Burn-In

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US Patent:
6426904, Jul 30, 2002
Filed:
Mar 9, 2001
Appl. No.:
09/803500
Inventors:
John E. Barth - Williston VT
Claude L. Bertin - South Burlington VT
Jeffrey H. Dreibelbis - Williston VT
Wayne F. Ellis - Jericho VT
Wayne J. Howell - Williston VT
Erik L. Hedberg - Essex Junction VT
Howard L. Kalter - Colchester VT
William R. Tonti - Essex Junction VT
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 2900
US Classification:
365201
Abstract:
Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer.

Integrated Test Structure And Method For Verification Of Microelectronic Devices

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US Patent:
6549150, Apr 15, 2003
Filed:
Sep 17, 2001
Appl. No.:
09/682536
Inventors:
Raymond J. Bulaga - Richmond VT
John K. Masi - Milton VT
Patrick W. Miller - Winooski VT
Mark S. Styduhar - Hinesburg VT
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03M 110
US Classification:
341120, 341118
Abstract:
An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.

Method For Test Optimization Using Historical And Actual Fabrication Test Data

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US Patent:
6618682, Sep 9, 2003
Filed:
Apr 20, 2001
Appl. No.:
09/838996
Inventors:
Raymond J. Bulaga - Richmond VT
Anne E. Gattiker - Austin TX
John L. Harris - South Burlington VT
Phillip J. Nigh - Williston VT
Leo A. Noel - Essex Junction VT
William J. Thibault - White River Junction VT
Jody J. Van Horn - Underhill VT
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01N 3700
US Classification:
702 84, 702 81
Abstract:
A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i. e. , process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Deterministic Random Lbist

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US Patent:
6708305, Mar 16, 2004
Filed:
Oct 18, 2000
Appl. No.:
09/691370
Inventors:
L. Owen Farnsworth - Lincoln VT
Brion L. Keller - Conklin NY
Bernd K. Koenemann - San Jose CA
Timothy J. Koprowski - Newburgh NY
Thomas J. Snethen - Endwell NY
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
714739, 714728
Abstract:
Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.

Method And Apparatus For Reduced Pin Count Package Connection Verification

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US Patent:
6724210, Apr 20, 2004
Filed:
Aug 22, 2001
Appl. No.:
09/682345
Inventors:
Michael L. Combs - Essex Junction VT
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3126
US Classification:
324765, 3241581, 714724
Abstract:
A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip with a weak driver and comparing the transition rise time with a threshold value. For an I/O with a faulty chip-to-package connection, the rise time is much faster than for an I/O with a completed chip-to-package connection. Additional impedances may also be added to the tester fixturing to increase the sensitivity of the test equipment to the capacitance of the I/O connections.

Method For Chip Testing

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US Patent:
6730529, May 4, 2004
Filed:
Jan 25, 1999
Appl. No.:
09/236183
Inventors:
Howard L. Kalter - Colchester VT
H. Bernhard Pogge - Hopewell Junction NY
George S. Prokop - Fishkill NY
Donald L. Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3126
US Classification:
438 17, 438 18
Abstract:
Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing.

System And Method To Predetermine A Bitmap Of A Self-Tested Embedded Array

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US Patent:
6754864, Jun 22, 2004
Filed:
Feb 22, 2001
Appl. No.:
09/791003
Inventors:
David V. Gangl - Essex Junction VT
Matthew Sean Grady - Burlington VT
David John Iverson - Underhill VT
Gary William Maier - Burlington VT
Robert Edward Shearer - Richmond VT
Donald Lawrence Wheater - Hinesburg VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
714733, 714732
Abstract:
A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.
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Donald L Wheater from Hinesburg, VT, age ~64 Get Report