Search

Dhruva J Acharyya

from Sudbury, MA
Age ~47
Get Report
Also known as:
Dhruvajyot Acharyya, Joyti D Acharyya, Dhuva Acharyya, Dhruvajyoti Acharyya, Jyoti A Dhruva
Phone and address:
14 Bigelow Dr, North Sudbury, MA 01776
Related to:
Vedashree AcharyyaD K NagArpita Nag, 46
Connected to:
Swapan Acharyya, 51Kevin M Achas, 37Quilin J Achat, 42Courtney N Achatz, 28Diane A Achatz, 62Andoni O Achaval, 50Maria D Achaval, 50Pedro A Achaval, 48Logan S Achay, 40John E Achbach, 59

Dhruva Acharyya Phones & Addresses

  • 14 Bigelow Dr, Sudbury, MA 01776
    • s
  • 9309 Palm Bay Cir, Raleigh, NC 27617
  • San Jose, CA
  • 2600 Gracy Farms Ln, Austin, TX 78758
  • Baltimore, MD
  • Hemet, CA
  • Des Moines, IA
  • 2600 Gracy Farms Ln APT 1234, Austin, TX 78758

Work

Company: Advantest Sep 2008 Position: Senior hardware design engineer in ate industry

Skills

Semiconductors • Hardware Architecture • Soc • Ic • Mixed Signal • Asic • Fpga • Analog • Debugging • Semiconductor Industry • Verilog • Test Engineering • Cmos • Rf • Eda • Failure Analysis • Product Engineering • Electronics • Vlsi • Embedded Systems • Digital Signal Processors • Perl • Simulations • Testing • Electrical Engineering • Pcb Design • C++ • Vlsi Test and Instrumentation

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Dhruva Acharyya Photo 1

Senior Hardware Design Engineer In Ate Industry

View page
Location:
14 Bigelow Dr, Sudbury, MA 01776
Industry:
Electrical/Electronic Manufacturing
Work:
Advantest
Senior Hardware Design Engineer In Ate Industry
Skills:
Semiconductors
Hardware Architecture
Soc
Ic
Mixed Signal
Asic
Fpga
Analog
Debugging
Semiconductor Industry
Verilog
Test Engineering
Cmos
Rf
Eda
Failure Analysis
Product Engineering
Electronics
Vlsi
Embedded Systems
Digital Signal Processors
Perl
Simulations
Testing
Electrical Engineering
Pcb Design
C++
Vlsi Test and Instrumentation

Publications

Us Patents

Characterizing Across-Die Process Variation

View page
US Patent:
7698079, Apr 13, 2010
Filed:
Nov 28, 2007
Appl. No.:
11/946571
Inventors:
Dhruva J. Acharyya - Austin TX, US
Kanak B. Agarwal - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 19/00
US Classification:
702 64, 324765, 716 5
Abstract:
Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles.

Method And Circuit For Measuring Operating And Leakage Current Of Individual Blocks Within An Array Of Test Circuit Blocks

View page
US Patent:
20080209285, Aug 28, 2008
Filed:
Feb 27, 2007
Appl. No.:
11/679346
Inventors:
Dhruva J. Acharyya - Austin TX, US
Sani R. Nassif - Austin TX, US
Rahul M. Rao - Elmsford NY, US
International Classification:
G01R 31/28
US Classification:
714724
Abstract:
A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.

System And Methods For Generating Unclonable Security Keys In Integrated Circuits

View page
US Patent:
20120319724, Dec 20, 2012
Filed:
Jan 12, 2011
Appl. No.:
13/513941
Inventors:
James Plusquellic - Albuquerque NM, US
Dhruva J. Acharyya - San Jose CA, US
Ryan L. Helinski - Albuquerque NM, US
Assignee:
STC.UNM - Albuquerque NM
International Classification:
H03K 19/00
H05K 3/00
US Classification:
326 8, 29829
Abstract:
A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

System And Methods For Generating Unclonable Security Keys In Integrated Circuits

View page
US Patent:
20140140505, May 22, 2014
Filed:
Nov 11, 2013
Appl. No.:
14/076541
Inventors:
James Plusquellic - Albuquerque NM, US
Dhruva J. Acharyya - San Jose CA, US
Ryan L. Helinski - Albuquerque NM, US
Assignee:
STC.UNM - Albuquerque NM
International Classification:
H04L 9/08
US Classification:
380 44
Abstract:
A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.
Control profile
Dhruva J Acharyya from Sudbury, MA, age ~47 Get Report