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Dhiraj Kumar

from Iselin, NJ
Age ~41
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Also known as:
Dhireg Kumar
Related to:
Sandeep KumariDev Kumar
Connected to:
Aarushi Kumar, 34Abhas Kumar, 34Adeep Kumar, 65Ahmed Kumar, 58Aina Kumar, 31Ajit Kumar, 49Akanksha Kumar, 29Aman Kumar, 55Amar Kumar, 60Amarjeet Kumar, 42

Dhiraj Kumar Phones & Addresses

  • Iselin, NJ

Work

Company: Hdfc bank Aug 2013 Position: Banking officer

Education

School / High School: V.K.Univarsity- Patna, Bihar 2004 Specialities: B.com in psychology

Resumes

Resumes

Dhiraj Kumar Photo 1

Dhiraj Kumar Patna, VA

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Work:
Hdfc Bank

Aug 2013 to 2000
Banking Officer
Hdfc Bank

Aug 2012 to 2000
Transaction Assistant
Education:
V.K.Univarsity
Patna, Bihar
2004 to 2007
B.com in psychology

Business Records

Name / Title
Company / Classification
Phones & Addresses
Dhiraj Kumar
Director Information Technology
Crecento Technologies Inc
Software Development & It Consulting
6 Kilmer Rd, Edison, NJ 08817
(732) 777-0233

Publications

Us Patents

Method And Apparatus For Bandwidth Efficient And Bounded Latency Packet Buffering

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US Patent:
20070011396, Jan 11, 2007
Filed:
Jun 30, 2005
Appl. No.:
11/172114
Inventors:
Kanwar Singh - Bangalore, IN
Dhiraj Kumar - Morristown NJ, US
Assignee:
UTStarcom, Inc. - Alameda CA
International Classification:
G06F 13/28
US Classification:
711105000
Abstract:
A system and method for buffering data packets in a data network device having a DRAM buffer are presented. When writing packets, the buffering system separates available memory channels into two groups corresponding to ingress and egress data. Based on the source of the data packets, data pages from the data packets are assigned to channels from either the ingress or egress group. Non-conflicting sets of addresses, called cachelines, are requested on each memory channel, and the data pages are evenly distributed over the assigned channels before being mapped to a cacheline. The number of read transactions currently being monitored by the system is controlled in order to reduce random packet read conflicts. Additionally, write and read transactions are grouped by an arbitration unit prior to being sent to the DRAM controller.

Method And System For Synchronous Page Addressing In A Data Packet Switch

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US Patent:
20080170571, Jul 17, 2008
Filed:
Jan 12, 2007
Appl. No.:
11/622699
Inventors:
Dhiraj Kumar - Morristown NJ, US
Kanwar Jit Singh - Panchkula, IN
International Classification:
H04L 12/56
US Classification:
370392, 370386, 370412
Abstract:
A method and system for synchronous page addressing in a data packet switch is provided. Within the packet switch, separate devices are responsible for storing a portion of a received data packet, and thus a view of used memory addresses seen by one device matches that seen by the others. Each device uses the same order of memory addresses to write data so that bytes of data are stored as a linked-list of pages. Maintaining the same sequence of page requests and sequence of free-page addresses to which to write these pages ensures consistent addressing of the portions of the data packet.

Streaming Buffer System For Variable Sized Data Packets

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US Patent:
20060268913, Nov 30, 2006
Filed:
May 27, 2005
Appl. No.:
11/139070
Inventors:
Kanwar Singh - Bangalore, IN
Dhiraj Kumar - Morristown NJ, US
Assignee:
UTStarcom, Inc. - Alameda CA
International Classification:
H04L 12/28
H04J 3/24
H04L 12/56
US Classification:
370412000, 370474000
Abstract:
A system for streaming incoming data packets into a buffer memory is presented. The system may receive incoming data packets over a variety of interfaces and separate the data packet into a header page and one or more data page. The system may interface with a header processor and send header pages to the header processor to be modified. Data pages from the incoming data packets are streamed to a central staging memory, allowing the use of a simple first-in-first-out (FIFO) buffer. The system may receive modified headers from the header processor and provide multiple copies of data packets for multicast or sampling purposes. Data packet copies may then be written to an external memory buffer over one or more external memory channels. The system may also provide an error recovery process to account for corrupt data packets streamed to the external memory buffer.

Wikipedia

Dhiraj Kumar Nath

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Dhiraj Kumar Nath is a Bangladeshi diplomat. He was named as an advisor of the interim caretaker government of Bangladesh in November 2006. Dhiraj Kumar

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Dhiraj Kumar from Iselin, NJ, age ~41 Get Report