William Rhoden

6434688, Aug 13, 2002

Sep 20, 1995

08/530617

William Desi Rhoden - Phoenix AZ
Rajeev Jayavant - Phoenix AZ

Koninklijke Philips Electronics N.V. - Eindhoven

G06F 1500

712 34, 345503, 345532

The present invention provides a low-cost computer system which includes a single sharable block of memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the âappetiteâ for main system memory (unlike that of a display memory) is difficult to satisfy, the memory can be addressed by reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements. In accordance with additional embodiments, improved efficiency of operation can be achieved to enhance concurrency between plural banks of memory when expansion memory is included. The addressable locations of the expansion memory can be mapped to the bottom of the available system address space, and addressable locations of any prior base system memory are moved above the expansion memory space.

56421362, Jun 24, 1997

Jun 7, 1996

8/661404

Rajeev Jayavant - Phoenix AZ
William Desi Rhoden - Phoenix AZ

VLSI Technology, Inc. - San Jose CA

G09G 524

345194

In a text mode of a display controller, for each character of the text, a plurality of multiple-byte words are stored in a memory buffer. Each multiple-byte word contains an ASCII character code for the character, font attribute information for the character and at least one font line for the character. For each character font line to be displayed on the monitor, a multiple byte word is read. The attribute information and a first character font line are extracted from the multiple byte word. The display controller then constructs a character scan line for the character based on the attribute information and the first character font line. The character scan line may then be displaying on the monitor.

54540763, Sep 26, 1995

Mar 2, 1994

8/204828

Bradley W. Cain - Mesa AZ
Rajeev Jayavant - Phoenix AZ
William D. Rhoden - Phoenix AZ

VLSI Technology, Inc. - San Jose CA

G06F 1200

395164

An image is written to a data frame buffer for display by a monitor. The image includes a repeated pattern. The present invention uses a repeated pattern cache which is not large enough to simultaneously contain an entire repeated pattern. When writing a pixel of the image, a horizontal pattern offset and a vertical pattern offset for a destination location of the pixel are determined. If a scan line for the repeated pattern which corresponds to the vertical pattern offset does not reside in the repeated pattern cache, the scan line for the repeated pattern which corresponds to the vertical pattern offset is fetched into the repeated pattern cache. When the scan line for the repeated pattern which corresponds to the vertical pattern offset resides in the repeated pattern cache, the pixel is accessed at a location in the repeated pattern cache at a location which corresponds to the horizontal pattern offset. The accessed pixel is written to the buffer.

56597150, Aug 19, 1997

May 8, 1996

8/646555

Shih-Ho Wu - Mesa AZ
William Desi Rhoden - Phoenix AZ
Mike Nakahara - Phoenix AZ

VLSI Technology, Inc. - San Jose CA

G06F 1200

39549701

A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.