Search

Derya Deniz

from Flushing, NY
Age ~65
Get Report
Also known as:
Denrya Deniz
Phone and address:
3440 79Th St, Flushing, NY 11372
Related to:
Ellen M Dimeco, 79Yasar DenizCarla DenizRagip DenizHumberto Manzo, 55Jessica Wilson, 45
Connected to:
Amber M Deniz, 37Ana M Deniz, 51Anil Deniz, 47Aslan T Deniz, 32Baris G Deniz, 27Cihat Deniz, 56Dustin D Deniz, 42Erdem Deniz, 39Erin K Deniz, 35Erkan Deniz, 39

Derya Deniz Phones & Addresses

  • 3440 79Th St, Jackson Heights, NY 11372
  • 13309 Booth Memorial Ave APT C12, Flushing, NY 11355 (718) 539-8370
  • 13309 Booth Memorial Ave, Flushing, NY 11355
  • 13420 57Th St, Flushing, NY 11355 (718) 961-6052
  • Forest Hills, NY
  • Nassau, NY

Publications

Us Patents

Silicidation And/Or Germanidation On Sige Or Ge By Cosputtering Ni And Ge And Using An Intralayer For Thermal Stability

View page
US Patent:
20130280907, Oct 24, 2013
Filed:
Apr 23, 2012
Appl. No.:
13/453740
Inventors:
Derya DENIZ - Delmar NY, US
Assignee:
GLOBAL FOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/3205
US Classification:
438664, 257E21296
Abstract:
Formation of a semiconductor device with NiGe or NiSiGe and with reduced consumption of underlying Ge or SiGe is provided. Embodiments include co-sputtering nickel (Ni) and germanium (Ge), forming a first Ni/Ge layer on a Ge or silicon germanium (SiGe) active layer, depositing titanium (Ti) on the first Ni/Ge or Ni/Si/Ge layer, forming a Ti intermediate layer, co-sputtering Ni and Ge on the Ti intermediate layer, forming a second Ni/Ge layer, and performing a rapid thermal anneal (RTA) process.

Semiconductor Device Incorporating A Multi-Function Layer Into Gate Stacks

View page
US Patent:
20140061812, Mar 6, 2014
Filed:
Sep 4, 2012
Appl. No.:
13/602839
Inventors:
Derya Deniz - Delmar NY, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 21/28
H01L 27/092
US Classification:
257369, 438592
Abstract:
Approaches are provided for forming a semiconductor device (e.g., a FET) having a multi-function layer (e.g., niobium carbide (NbC)) that serves as a work function layer and a gate metal layer in gate stacks of solid state applications. By introducing a single layer with multiple functions, total number of layers that needs processing (e.g., recessing) may be decreased. As such, the complexity of device integration and resulting complications may be reduced.

Fabrication Of Nickel Free Silicide For Semiconductor Contact Metallization

View page
US Patent:
20150061032, Mar 5, 2015
Filed:
Nov 10, 2014
Appl. No.:
14/536737
Inventors:
- GRAND CAYMAN, KY
Derya DENIZ - Troy NY, US
Assignee:
GLOBALFOUNDRIES INC. - GRAND CAYMAN
International Classification:
H01L 29/51
H01L 29/78
US Classification:
257369
Abstract:
A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Methods Of Forming Stressed Fin Channel Structures For Finfet Semiconductor Devices

View page
US Patent:
20150041906, Feb 12, 2015
Filed:
Aug 6, 2013
Appl. No.:
13/960200
Inventors:
- Grand Cayman, KY
Derya Deniz - Troy NY, US
Abner Bello - Clifton Park NY, US
Abhijeet Paul - Albany NY, US
Robert J. Miller - Yorktown Heights NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/8238
H01L 27/092
US Classification:
257369, 438199
Abstract:
One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Fabrication Of Nickel Free Silicide For Semiconductor Contact Metallization

View page
US Patent:
20140361375, Dec 11, 2014
Filed:
Jun 5, 2013
Appl. No.:
13/910370
Inventors:
- Grand Cayman, KY
Derya DENIZ - Troy NY, US
International Classification:
H01L 21/283
H01L 29/45
US Classification:
257369, 438655
Abstract:
A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Semiconductor Device Incorporating A Multi-Function Layer Into The Gate Stacks

View page
US Patent:
20140361379, Dec 11, 2014
Filed:
Aug 22, 2014
Appl. No.:
14/466103
Inventors:
- Grand Cayman, KY
Derya Deniz - Delmar NY, US
International Classification:
H01L 27/092
H01L 29/49
US Classification:
257369
Abstract:
Approaches are provided for forming a semiconductor device (e.g., a FET) having a multi-function layer (e.g., niobium carbide (NbC)) that serves as a work function layer and a gate metal layer in gate stacks of solid state applications. By introducing a single layer with multiple functions, total number of layers that needs processing (e.g., recessing) may be decreased. As such, the complexity of device integration and resulting complications may be reduced.

Finfet Channel Stress Using Tungsten Contacts In Raised Epitaxial Source And Drain

View page
US Patent:
20140319614, Oct 30, 2014
Filed:
Apr 25, 2013
Appl. No.:
13/870854
Inventors:
- Grand Cayman, KY
Abner BELLO - Clifton Park NY, US
Vimal K. KAMINENI - Albany NY, US
Derya DENIZ - Troy NY, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 29/66
H01L 29/78
US Classification:
257365, 438283
Abstract:
Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.
Control profile
Derya Deniz from Flushing, NY, age ~65 Get Report