Denton G Wicklund

55303021, Jun 25, 1996

Jan 13, 1994

8/180623

John D. Hamre - Plymouth MN
Denton G. Wicklund - Delano MN
Steven D. Barkley - Roseville MN

Network Systems Corporation - Minneapolis MN

H01J 1300

307147

A circuit board capable of live-insertion or hot-swapping into a live chassis backplane. The circuit board is provided with a power control circuitry for gracefully ramping up board power after insertion, or gracefully removing power just prior to physical removal of a circuit board from the board slot. A pair of ejector levers are provided on each side of the circuit board. A push button switch is provided proximate one ear thereof and is selectively opened or closed depending upon the position of an ejector cover which can be secured thereover in an interlocking relationship. Upon retraction of the extractor cover, the switch is opened, and the converse applies. Power MOSFETs are provided between the card edge and the board power busses which are gracefully turned on and off as a function of the switch position. A high-side gate driver provides an increased bias voltage, which bias voltage is communicated through the closed switch to the gates of the MOSFETs. An RC network is coupled to the MOSFET gate to determine the time constant at which bias voltage will be ramped up or ramped down to correspondingly ramp power up or down to the circuit board power busses.

52967484, Mar 22, 1994

Jun 24, 1992

7/903692

Denton G. Wicklund - Delano MN
John P. Mullaney - Minneapolis MN

Network Systems Corporation - Minneapolis MN

H05K 720

3073031

A seamless clock distribution scheme for a system incorporating sequential digital logic devices disposed on multiple parallel boards for reducing or substantially eliminating skew. The multiple parallel boards are positioned on and project outward from one side of a centerplane. A single clock board, generating multiple copies of the system clock and mounted at a right angle to the parallel boards on the opposite side of the centerplane are connected by shared pins passing through apertures formed in the centerplane. This shared pin connection allows for simple, though near-ideal transmission of the clock signal copies between the parallel logic boards and the clock board with a minimum mismatch of the clock signal between two parallel boards.