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Deepak Kataria

from Leesburg, VA
Age ~57
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Also known as:
Deepak Lataria, Deepak Katara, Deepak Katrina, Kataria Deepak, A A
Phone and address:
40378 Oatlands Mill Rd, Leesburg, VA 20175
Related to:
Michael Joseph Ball, 74Nimit Jain, 35Jennifer Jain, 28Sudha KatariaNeelam Jain, 60Alpna J Doshi, 57Richard P Koldewey, 81Shantilal JainVijay JainArchana Jain, 56Jai K Jain, 66Saroj JainNisha J Bindal, 51
Connected to:
Balvinder S Kataria, 70Dimple Kataria, 38Harpreet Kataria, 49Isha Kataria, 27Manish C Kataria, 54Mohan Kataria, 64N Kataria, 60Reena Kataria, 42Sam Kataria, 54Sheena G Kataria, 40

Deepak Kataria Phones & Addresses

  • 40378 Oatlands Mill Rd, Leesburg, VA 20175
  • 672 Old Hunt Way, Herndon, VA 20170
  • 3009 Jonquilla Ct, Herndon, VA 20171 (703) 264-1834
  • Sterling, VA
  • Randolph, NJ
  • 5472 Fuller Dr, Glen Allen, VA 23059
  • Vienna, VA
  • Falls Church, VA
  • Columbia, MD

Business Records

Name / Title
Company / Classification
Phones & Addresses
Deepak Kataria
Principal
Ip Junction, Inc
Business Consulting Services · Business Consulting, Nec, Nsk
9 Jenna Dr, Bridgewater, NJ 08807
Deepak Kataria
VP Systems
Razorsight
Telecommunications · Custom Computer Programing
12012 Sunset Hl Rd SUITE 910, Reston, VA 20190
1750 Presidents St SUITE 205, Reston, VA 20190
3975 Fair Rdg Dr, Fairfax, VA 22033
(703) 995-5900, (703) 995-5901
Deepak Kataria
President
Magnata, Inc
Software & Technology Services Organization That Is Focused On Creating Solutions to Make Our Customers Lives Simpler
5472 Fuller Dr, Glen Allen, VA 23059

Publications

Us Patents

Quality Of Service Based Path Selection For Connection-Oriented Networks

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US Patent:
6661797, Dec 9, 2003
Filed:
Feb 28, 2000
Appl. No.:
09/514725
Inventors:
Ashish Goel - Marine Del Rey CA
Deepak Kataria - Edison NJ
Dimitris Logothetis - North Bergen NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H04L 1228
US Classification:
37039521, 709240
Abstract:
Arrangements and methods for efficiently selecting an optimum connection path that meets user specified delay requirements with enhanced efficiency. In a basic aspect, a method is implemented by one of a plurality of algorithms to meet user QoS specifications. The user not only specifies a delay threshold T for the incoming request but also specifies a delay threshold tolerance for the path delay that will satisfy him. Two implementations are disclosed. The first is termed non-iterative and sets scaling factor =min (T, (n-1)/ ), where n is a number of links in a shortest path, scales all the relevant delay parameters by /T, truncates all the scaled values to integers, and uses a dynamic programming algorithm to accumulate the total of resulting link delay parameters values for each possible shortest path. The second method, termed iterative, is similar, except that it sets T. Then if the scaling, truncation, and accumulation steps do not satisfy customer specifications, the next iteration doubles.

Quality Of Service Based Path Selection For Connection-Oriented Networks

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US Patent:
6687229, Feb 3, 2004
Filed:
Nov 6, 1998
Appl. No.:
09/188023
Inventors:
Deepak Kataria - Edison NJ, 08817
Dimitris Logothetis - North Bergen NJ, 07047
Santhanam Srinivasan - Holmedel NJ, 07733
Malathi Veeraraghavan - Atlantic Highlands NJ, 07716
International Classification:
H04L 1226
US Classification:
370238, 370351
Abstract:
Arrangements and methods for improving the probability of finding a connection path that meets user specified delay requirements. The improvements offer packet switches enhanced path selection that will improve the resource utilization of networks, both flat networks and hierarchical networks incorporating such switches. The latter type of networks run the path selection algorithm in the PNNI v1. 0 standard where the packet switches are asynchronous transfer mode switches. Two modes of enhanced delay-based path selection are based on two different accumulation methods, namely an additive method and an asymptotic method.

Buffer Management For Merging Packets Of Virtual Circuits

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US Patent:
7177279, Feb 13, 2007
Filed:
Apr 24, 2002
Appl. No.:
10/131577
Inventors:
Deepak Kataria - Edison NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04J 3/14
US Classification:
370235, 370397, 37039541, 370412
Abstract:
In one embodiment, an apparatus for coordinating merging of packets for one or more virtual circuits (VGs). Each packet of a VC comprising a sequence of cells terminates with an end of packet (EOP) cell. The apparatus comprises one or more buffers, a buffer controller, and a merge processor. Each buffer is configured to receive cells of an associated VC and a threshold value based on traffic of the VC. When a number of cells of a packet in a buffer exceeds the corresponding dynamic threshold value, a corresponding flag of the buffer is set. The buffer controller is configured to drop all cells of the current packet in response to a set flag of a corresponding buffer. The merge processor services each buffer in accordance with a scheduling method to transfer one or more packets from each buffer to an output packet stream.

Methods And Apparatus For Minimizing Sequence Identifier Difference Of Simultaneously Transmitted Cells

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US Patent:
7633962, Dec 15, 2009
Filed:
Jul 29, 2005
Appl. No.:
11/193799
Inventors:
Deepak Kataria - Edison NJ, US
Codrut Radu Radulescu - Hillsdale NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 12/54
US Classification:
370428, 370394, 3703953, 370412
Abstract:
A method of minimizing SID difference of simultaneously transmitted cells in two or more data communication lines is provided. A data transmission speed of each of the two or more data communication lines is identified. A fullness threshold of at least one buffer of two or more buffers in a transmit node is configured in relation to a size of a data cell for transmission. The two or more buffers correspond to respective ones of the two or more data communication lines. The at least one buffer communicates with a given one of the two or more data communication lines having a data transmission speed slower than another of the two or more data communication lines. One or more data cells for transmission are assigned to the two or more buffers of the two or more data communication lines at the transmit node. The one or more data cells are transmitted from the transmit node to a receive node in accordance with the data transmission speeds of the two or more data communication lines. The fullness threshold of the at least one buffer controls assignment of data cells to the at least one buffer during data cell transmission on the given data communication line and minimizes SID difference of simultaneously transmitted cells in the two or more data communication lines.

Methods And Apparatus For Timing Synchronization In Packet Networks

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US Patent:
7711009, May 4, 2010
Filed:
Sep 29, 2006
Appl. No.:
11/536848
Inventors:
Deepak Kataria - Bridgewater NJ, US
Chengzhou Li - Whitehall PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04J 3/06
US Classification:
370503, 375373
Abstract:
Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

Methods And Apparatus For Reorganizing Cells Buffered After Transmission

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US Patent:
7924857, Apr 12, 2011
Filed:
Jan 5, 2006
Appl. No.:
11/326047
Inventors:
Deepak Kataria - Edison NJ, US
Codrut Radu Radulescu - Hillsdale NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 12/56
US Classification:
370412, 370368, 370394, 370420, 370249, 711162
Abstract:
A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.

Methods And Apparatus For Prevention Of Excessive Control Message Traffic In A Digital Networking System

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US Patent:
7971247, Jun 28, 2011
Filed:
Jul 21, 2006
Appl. No.:
11/459035
Inventors:
Deepak Kataria - Edison NJ, US
Seong-Hwan Kim - Allentown PA, US
Sundar Vedantham - Orwigsburg PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 9/32
US Classification:
726 22, 726 23
Abstract:
Methods and apparatus for use with an integrated circuit device of a processing device of a network node of a digital networking system, configured to monitor one or more control messages received at the processing device from each of a plurality of CPE devices, and limiting the one or more control messages to one or more specified rates for a specified duration. The integrated circuit device is further configured to provide one or more data channels to the plurality of CPE devices from the processing device in response to the one or more control messages processed at the processing device.

Multi-Stage Scheduler With Processor Resource And Bandwidth Resource Allocation

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US Patent:
8379518, Feb 19, 2013
Filed:
Jan 23, 2007
Appl. No.:
11/625884
Inventors:
Deepak Kataria - Bridgewater NJ, US
Chengzhou Li - Whitehall PA, US
Assignee:
Agere Systems LLC - Allentown PA
International Classification:
G01R 31/08
US Classification:
370230
Abstract:
A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.
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Deepak Kataria from Leesburg, VA, age ~57 Get Report